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Found 4 papers, 0 papers with code
SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators
Systolic array has emerged as a prominent architecture for Deep Neural Network (DNN) hardware accelerators, providing high-throughput and low-latency performance essential for deploying DNNs across diverse applications.
Special Session: Approximation and Fault Resiliency of DNN Accelerators
We propose to use approximate (AxC) arithmetic circuits to agilely emulate errors in hardware without performing fault injection on the DNN.
Hitless memory-reconfigurable photonic reservoir computing architecture
Reservoir computing is an analog bio-inspired computation model for efficiently processing time-dependent signals, the photonic implementations of which promise a combination of massive parallel information processing, low power consumption, and high speed operation.
Fast Exploration of Weight Sharing Opportunities for CNN Compression
The computational workload involved in Convolutional Neural Networks (CNNs) is typically out of reach for low-power embedded devices.
