Search Results for author: Alexander J. Edwards

Found 6 papers, 0 papers with code

Deep Neuromorphic Networks with Superconducting Single Flux Quanta

no code implementations21 Sep 2023 Gleb Krylov, Alexander J. Edwards, Joseph S. Friedman, Eby G. Friedman

Neuromorphic circuits are a promising approach to computing where techniques used by the brain to achieve high efficiency are exploited.

Neuromorphic Hebbian learning with magnetic tunnel junction synapses

no code implementations21 Aug 2023 Peng Zhou, Alexander J. Edwards, Frederick B. Mancoff, Sanjeev Aggarwal, Stephen K. Heinrich-Barna, Joseph S. Friedman

Neuromorphic computing aims to mimic both the function and structure of biological neural networks to provide artificial intelligence with extreme efficiency.

Handwritten Digit Recognition

Experimental Demonstration of Neuromorphic Network with STT MTJ Synapses

no code implementations9 Dec 2021 Peng Zhou, Alexander J. Edwards, Fred B. Mancoff, Dimitri Houssameddine, Sanjeev Aggarwal, Joseph S. Friedman

We present the first experimental demonstration of a neuromorphic network with magnetic tunnel junction (MTJ) synapses, which performs image recognition via vector-matrix multiplication.

Handwritten Digit Recognition

Analog Seizure Detection for Implanted Responsive Neurostimulation

no code implementations11 Jun 2021 Abbas A. Zaki, Noah C. Parker, Tae-Yoon Kim, Sam Ishak, Ty E. Stovall, Genchang Peng, Hina Dave, Jay Harvey, Mehrdad Nourani, Xuan Hu, Alexander J. Edwards, Joseph S. Friedman

Similarly, power calculations were performed, demonstrating that the system uses $6. 5 \mu W$ per channel, which when compared to the state-of-the-art NeuroPace system would increase battery life by up to $50 \%$.

Bayesian Inference Seizure Detection

Reservoir Computing with Planar Nanomagnet Arrays

no code implementations24 Mar 2020 Peng Zhou, Nathan R. McDonald, Alexander J. Edwards, Lisa Loomis, Clare D. Thiem, Joseph S. Friedman

Reservoir computing is an emerging methodology for neuromorphic computing that is especially well-suited for hardware implementations in size, weight, and power (SWaP) constrained environments.

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