Search Results for author: Anand Raghunathan

Found 25 papers, 4 papers with code

Ev-Edge: Efficient Execution of Event-based Vision Algorithms on Commodity Edge Platforms

no code implementations23 Mar 2024 Shrihari Sridharan, Surya Selvam, Kaushik Roy, Anand Raghunathan

On several state-of-art networks for a range of autonomous navigation tasks, Ev-Edge achieves 1. 28x-2. 05x improvements in latency and 1. 23x-2. 15x in energy over an all-GPU implementation on the NVIDIA Jetson Xavier AGX platform for single-task execution scenarios.

Autonomous Navigation Event-based vision +1

Input Compression with Positional Consistency for Efficient Training and Inference of Transformer Neural Networks

1 code implementation22 Nov 2023 Amrit Nagarajan, Anand Raghunathan

This leads to smaller input sequences being processed by the Transformer, and hence faster training, while also alleviating overfitting by presenting each input with different compression levels.

Data Augmentation

Evaluation of STT-MRAM as a Scratchpad for Training in ML Accelerators

no code implementations3 Aug 2023 Sourjya Roy, Cheng Wang, Anand Raghunathan

We devised a cross-layer simulation framework to evaluate the effectiveness of STT-MRAM as a scratchpad replacing SRAM in a systolic-array-based DNN accelerator.

X-Former: In-Memory Acceleration of Transformers

no code implementations13 Mar 2023 Shrihari Sridharan, Jacob R. Stevens, Kaushik Roy, Anand Raghunathan

Transformers have achieved great success in a wide variety of natural language processing (NLP) tasks due to the attention mechanism, which assigns an importance score for every word relative to other words in a sequence.

Blocking

Approximate Computing and the Efficient Machine Learning Expedition

no code implementations2 Oct 2022 Jörg Henkel, Hai Li, Anand Raghunathan, Mehdi B. Tahoori, Swagath Venkataramani, Xiaoxuan Yang, Georgios Zervakis

In this work, we enlighten the synergistic nature of AxC and ML and elucidate the impact of AxC in designing efficient ML systems.

Descriptive

A Co-design view of Compute in-Memory with Non-Volatile Elements for Neural Networks

no code implementations3 Jun 2022 Wilfried Haensch, Anand Raghunathan, Kaushik Roy, Bhaswar Chakrabart, Charudatta M. Phatak, Cheng Wang, Supratik Guha

In the second part, we review what is knows about the different new non-volatile memory materials and devices suited for compute in-memory, and discuss the outlook and challenges.

Efficient Ensembles of Graph Neural Networks

no code implementations29 Sep 2021 Amrit Nagarajan, Jacob R. Stevens, Anand Raghunathan

In this work, we leverage the unique characteristics of GNNs to overcome these overheads, creating efficient ensemble GNNs that are faster than even single models at inference time.

Ensemble Learning Network Pruning +2

Specialized Transformers: Faster, Smaller and more Accurate NLP Models

no code implementations29 Sep 2021 Amrit Nagarajan, Sanchari Sen, Jacob R. Stevens, Anand Raghunathan

We propose a Specialization framework to create optimized transformer models for a given downstream task.

Hard Attention Quantization

InterTrain: Accelerating DNN Training using Input Interpolation

no code implementations29 Sep 2021 Sarada Krithivasan, Swagath Venkataramani, Sanchari Sen, Anand Raghunathan

This is because the efficacy of learning on interpolated inputs is reduced by the interference between the forward/backward propagation of their constituent inputs.

Accelerating DNN Training through Selective Localized Learning

no code implementations1 Jan 2021 Sarada Krithivasan, Sanchari Sen, Swagath Venkataramani, Anand Raghunathan

The trend in the weight updates made to the transition layer across epochs is used to determine how the boundary betweenSGD and localized updates is shifted in future epochs.

Ax-BxP: Approximate Blocked Computation for Precision-Reconfigurable Deep Neural Network Acceleration

no code implementations25 Nov 2020 Reena Elangovan, Shubham Jain, Anand Raghunathan

To efficiently support precision re-configurability in DNN accelerators, we introduce an approximate computing method wherein DNN computations are performed block-wise (a block is a group of bits) and re-configurability is supported at the granularity of blocks.

AxFormer: Accuracy-driven Approximation of Transformers for Faster, Smaller and more Accurate NLP Models

1 code implementation7 Oct 2020 Amrit Nagarajan, Sanchari Sen, Jacob R. Stevens, Anand Raghunathan

We propose AxFormer, a systematic framework that applies accuracy-driven approximations to create optimized transformer models for a given downstream task.

Hard Attention Quantization +1

Sparsity Turns Adversarial: Energy and Latency Attacks on Deep Neural Networks

no code implementations14 Jun 2020 Sarada Krithivasan, Sanchari Sen, Anand Raghunathan

We also evaluate the impact of the attack on a sparsity-optimized DNN accelerator and demonstrate degradations up to 1. 59x in latency, and also study the performance of the attack on a sparsity-optimized general-purpose processor.

Computational Efficiency Quantization

EMPIR: Ensembles of Mixed Precision Deep Networks for Increased Robustness against Adversarial Attacks

1 code implementation ICLR 2020 Sanchari Sen, Balaraman Ravindran, Anand Raghunathan

Our results indicate that EMPIR boosts the average adversarial accuracies by 42. 6%, 15. 2% and 10. 5% for the DNN models trained on the MNIST, CIFAR-10 and ImageNet datasets respectively, when compared to single full-precision models, without sacrificing accuracy on the unperturbed inputs.

Self-Driving Cars

Pruning Filters while Training for Efficiently Optimizing Deep Learning Networks

no code implementations5 Mar 2020 Sourjya Roy, Priyadarshini Panda, Gopalakrishnan Srinivasan, Anand Raghunathan

Our results for VGG-16 trained on CIFAR10 shows that L1 normalization provides the best performance among all the techniques explored in this work with less than 1% drop in accuracy after pruning 80% of the filters compared to the original network.

TxSim:Modeling Training of Deep Neural Networks on Resistive Crossbar Systems

no code implementations25 Feb 2020 Sourjya Roy, Shrihari Sridharan, Shubham Jain, Anand Raghunathan

To address this challenge, there is a need for tools that can model the functional impact of non-idealities on DNN training and inference.

Computational Efficiency

Gradual Channel Pruning while Training using Feature Relevance Scores for Convolutional Neural Networks

1 code implementation23 Feb 2020 Sai Aparna Aketi, Sourjya Roy, Anand Raghunathan, Kaushik Roy

To address all the above issues, we present a simple-yet-effective gradual channel pruning while training methodology using a novel data-driven metric referred to as feature relevance score.

Model Compression

TiM-DNN: Ternary in-Memory accelerator for Deep Neural Networks

no code implementations15 Sep 2019 Shubham Jain, Sumeet Kumar Gupta, Anand Raghunathan

The use of lower precision has emerged as a popular technique to optimize the compute and storage requirements of complex Deep Neural Networks (DNNs).

Image Classification Language Modelling

Pack and Detect: Fast Object Detection in Videos Using Region-of-Interest Packing

no code implementations5 Sep 2018 Athindran Ramesh Kumar, Balaraman Ravindran, Anand Raghunathan

Based on these observations, we propose Pack and Detect (PaD), an approach to reduce the computational requirements of object detection in videos.

Object object-detection +4

RxNN: A Framework for Evaluating Deep Neural Networks on Resistive Crossbars

no code implementations31 Aug 2018 Shubham Jain, Abhronil Sengupta, Kaushik Roy, Anand Raghunathan

We present RxNN, a fast and accurate simulation framework to evaluate large-scale DNNs on resistive crossbar systems.

SparCE: Sparsity aware General Purpose Core Extensions to Accelerate Deep Neural Networks

no code implementations7 Nov 2017 Sanchari Sen, Shubham Jain, Swagath Venkataramani, Anand Raghunathan

SparCE consists of 2 key micro-architectural enhancements- a Sparsity Register File (SpRF) that tracks zero registers and a Sparsity aware Skip Address (SASA) table that indicates instructions to be skipped.

Attribute

DyVEDeep: Dynamic Variable Effort Deep Neural Networks

no code implementations4 Apr 2017 Sanjay Ganapathy, Swagath Venkataramani, Balaraman Ravindran, Anand Raghunathan

Complementary to these approaches, DyVEDeep is a dynamic approach that exploits the heterogeneity in the inputs to DNNs to improve their compute efficiency with comparable classification accuracy.

Multiplier-less Artificial Neurons Exploiting Error Resiliency for Energy-Efficient Neural Computing

no code implementations27 Feb 2016 Syed Shakib Sarwar, Swagath Venkataramani, Anand Raghunathan, Kaushik Roy

Multipliers consume most of the processing energy in the digital neurons, and thereby in the hardware implementations of artificial neural networks.

Energy-Efficient Object Detection using Semantic Decomposition

no code implementations29 Sep 2015 Priyadarshini Panda, Swagath Venkataramani, Abhronil Sengupta, Anand Raghunathan, Kaushik Roy

We propose a 2-stage hierarchical classification framework, with increasing levels of complexity, wherein the first stage is trained to recognize the broad representative semantic features relevant to the object of interest.

General Classification Object +2

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