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Found 6 papers, 1 papers with code
RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU
As AI-based applications become pervasive, CPU vendors are starting to incorporate matrix engines within the datapath to boost efficiency.
AIRCHITECT: Learning Custom Architecture Design and Mapping Space
We design and train a custom network architecture called AIRCHITECT, which is capable of learning the architecture design space with as high as 94. 3% test accuracy and predicting optimal configurations which achieve on average (GeoMean) of 99. 9% the best possible performance on a test dataset with $10^5$ GEMM workloads.
Self-Adaptive Reconfigurable Arrays (SARA): Using ML to Assist Scaling GEMM Acceleration
We demonstrate an instance of SARA with an accelerator we call SAGAR, which introduces a novel reconfigurable systolic array that can be configured to work as a distributed collection of smaller arrays of various sizes or as a single array with flexible aspect ratios.
CLAN: Continuous Learning using Asynchronous Neuroevolution on Commodity Edge Devices
The true impact of AI can only be fully realized if we can have AI agents continuously interacting with the real world and solving everyday problems.
SCALE-Sim: Systolic CNN Accelerator
Systolic Arrays are one of the most popular compute substrates within Deep Learning accelerators today, as they provide extremely high efficiency for running dense matrix multiplications.
Distributed, Parallel, and Cluster Computing Hardware Architecture
GeneSys: Enabling Continuous Learning through Neural Network Evolution in Hardware
EvE can evolve the topology and weights of neural networks completely in hardware for the task at hand, without requiring hand-optimization or backpropagation training.
