Search Results for author: Artur Podobas

Found 7 papers, 4 papers with code

FFTc: An MLIR Dialect for Developing HPC Fast Fourier Transform Libraries

no code implementations14 Jul 2022 Yifei He, Artur Podobas, Måns I. Andersson, Stefano Markidis

Discrete Fourier Transform (DFT) libraries are one of the most critical software components for scientific computing.

Higgs Boson Classification: Brain-inspired BCPNN Learning with StreamBrain

1 code implementation14 Jul 2021 Martin Svedin, Artur Podobas, Steven W. D. Chien, Stefano Markidis

One of the most promising approaches for data analysis and exploration of large data sets is Machine Learning techniques that are inspired by brain models.

Classification

Automatic Particle Trajectory Classification in Plasma Simulations

no code implementations11 Oct 2020 Stefano Markidis, Ivy Peng, Artur Podobas, Itthinat Jongsuebchoke, Gabriel Bengtsson, Pawel Herman

Our overall goal is to provide a general workflow for exploring particle trajectory space and automatically classifying particle trajectories from plasma simulations in an unsupervised manner.

Classification Clustering +1

A Survey on Coarse-Grained Reconfigurable Architectures from a Performance Perspective

no code implementations9 Apr 2020 Artur Podobas, Kentaro Sano, Satoshi Matsuoka

With the end of both Dennard's scaling and Moore's law, computer users and researchers are aggressively exploring alternative forms of computing in order to continue the performance scaling that we have come to enjoy.

Hardware Architecture A.1; B.0; C.1; C.3

High-Performance High-Order Stencil Computation on FPGAs Using OpenCL

1 code implementation14 Feb 2020 Hamid Reza Zohouri, Artur Podobas, Satoshi Matsuoka

We show that despite the higher computation intensity and on-chip memory requirement of such stencils compared to first-order ones, our design technique with combined spatial and temporal blocking remains effective.

Distributed, Parallel, and Cluster Computing

Combined Spatial and Temporal Blocking for High-Performance Stencil Computation on FPGAs Using OpenCL

1 code implementation1 Feb 2018 Hamid Reza Zohouri, Artur Podobas, Satoshi Matsuoka

Furthermore, we estimate that the upcoming Stratix 10 devices can achieve a performance of up to 3. 5 TFLOP/s and 1. 6 TFLOP/s for 2D and 3D stencil computation, respectively.

Distributed, Parallel, and Cluster Computing Hardware Architecture

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