Search Results for author:
Found 2 papers, 0 papers with code
A Multi-Expert Large Language Model Architecture for Verilog Code Generation
Recently, there has been a surging interest in using large language models (LLMs) for Verilog code generation.
Mining SoC Message Flows with Attention Model
High-quality system-level message flow specifications are necessary for comprehensive validation of system-on-chip (SoC) designs.
Cannot find the paper you are looking for? You can
Submit a new open access paper.
