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Found 15 papers, 2 papers with code
ChipNeMo: Domain-Adapted LLMs for Chip Design
ChipNeMo aims to explore the applications of large language models (LLMs) for industrial chip design.
VerilogEval: Evaluating Large Language Models for Verilog Code Generation
The increasing popularity of large language models (LLMs) has paved the way for their application in diverse domains.
HEAT: Hardware-Efficient Automatic Tensor Decomposition for Transformer Compression
Transformers have attained superior performance in natural language processing and computer vision.
An Adversarial Active Sampling-based Data Augmentation Framework for Manufacturable Chip Design
These synthetic mask images will augment the original limited training dataset used to finetune the lithography model for improved performance.
Large Scale Mask Optimization Via Convolutional Fourier Neural Operator and Litho-Guided Self Training
Machine learning techniques have been extensively studied for mask optimization problems, aiming at better mask printability, shorter turnaround time, better mask manufacturability, and so on.
Optimal Clipping and Magnitude-aware Differentiation for Improved Quantization-aware Training
Data clipping is crucial in reducing noise in quantization operations and improving the achievable accuracy of quantization-aware training (QAT).
Generic Lithography Modeling with Dual-band Optics-Inspired Neural Networks
Lithography simulation is a critical step in VLSI design and optimization for manufacturability.
GATSPI: GPU Accelerated Gate-Level Simulation for Power Improvement
In this paper, we present GATSPI, a novel GPU accelerated logic gate simulator that enables ultra-fast power estimation for industry sized ASIC designs with millions of gates.
NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning
High quality standard cell layout automation in advanced technology nodes is still challenging in the industry today because of complex design rules.
LNS-Madam: Low-Precision Training in Logarithmic Number System using Multiplicative Weight Update
Representing deep neural networks (DNNs) in low-precision is a promising approach to enable efficient acceleration and memory reduction.
VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference
4-bit weights and 8-bit activations achieve near-full-precision accuracy for both BERT-base and BERT-large on SQuAD while reducing area by 26% compared to an 8-bit baseline.
FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning
Experimental results on benchmark circuits show that our approach achieves 25% improvement in design quality or 37% reduction in sampling cost compared to random forest method, which is the kernel of a highly cited previous work.
PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network
Moreover, the proposed CNN model is general and transferable to different designs.
Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference
We also introduce an energy model to predict the requirements of high-accuracy AMS hardware running large networks and use it to show that for ADC-dominated designs, there is a direct tradeoff between energy efficiency and network accuracy.
SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks
Convolutional Neural Networks (CNNs) have emerged as a fundamental technology for machine learning.
