Ordering Chaos: Memory-Aware Scheduling of Irregularly Wired Neural Networks for Edge Devices

no code implementations • 4 Mar 2020 • Byung Hoon Ahn, Jinwon Lee, Jamie Menjay Lin, Hsin-Pai Cheng, Jilei Hou, Hadi Esmaeilzadeh

To address this standing issue, we present a memory-aware compiler, dubbed SERENITY, that utilizes dynamic programming to find a sequence that finds a schedule with optimal memory footprint.

Neural Architecture Search Scheduling

Chameleon: Adaptive Code Optimization for Expedited Deep Neural Network Compilation

1 code implementation • ICLR 2020 • Byung Hoon Ahn, Prannoy Pilligundla, Amir Yazdanbakhsh, Hadi Esmaeilzadeh

This solution dubbed Chameleon leverages reinforcement learning whose solution takes fewer steps to converge, and develops an adaptive sampling algorithm that not only focuses on the costly samples (real hardware measurements) on representative points but also uses a domain-knowledge inspired logic to improve the samples itself.

Reinforcement Learning and Adaptive Sampling for Optimized DNN Compilation

1 code implementation • 30 May 2019 • Byung Hoon Ahn, Prannoy Pilligundla, Hadi Esmaeilzadeh

Further experiments also confirm that our adaptive sampling can even improve AutoTVM's simulated annealing by 4. 00x.

Clustering reinforcement-learning +1