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Found 32 papers, 16 papers with code
An Efficient Training Framework for Reversible Neural Architectures
In this work, we formulate the decision problem for reversible operators with training time as the objective function and memory usage as the constraint.
Subgraph Extraction-based Feedback-guided Iterative Scheduling for HLS
This paper proposes ISDC, a novel feedback-guided iterative system of difference constraints (SDC) scheduling algorithm for high-level synthesis (HLS).
QuantumSEA: In-Time Sparse Exploration for Noise Adaptive Quantum Circuits
To address these two pain points, we propose QuantumSEA, an in-time sparse exploration for noise-adaptive quantum circuits, aiming to achieve two key objectives: (1) implicit circuits capacity during training - by dynamically exploring the circuit's sparse connectivity and sticking a fixed small number of quantum gates throughout the training which satisfies the coherence time and enjoy light noises, enabling feasible executions on real quantum devices; (2) noise robustness - by jointly optimizing the topology and parameters of quantum circuits under real device noise models.
Practical Layout-Aware Analog/Mixed-Signal Design Automation with Bayesian Neural Networks
Our efficient algorithm solves the post-layout performance optimization problem where simulations are known to be expensive.
Transformer-QEC: Quantum Error Correction Code Decoding with Transferable Transformers
Quantum Error Correction (QEC) mitigates this by employing redundancy, distributing quantum information across multiple data qubits and utilizing syndrome qubits to monitor their states for errors.
RobustState: Boosting Fidelity of Quantum State Preparation via Noise-Aware Variational Training
Arbitrary state preparation algorithms can be broadly categorized into arithmetic decomposition (AD) and variational quantum state preparation (VQSP).
M3ICRO: Machine Learning-Enabled Compact Photonic Tensor Core based on PRogrammable Multi-Operand Multimode Interference
The programmable MOMMI leverages the intrinsic light propagation principle, providing a single-device programmable matrix unit beyond the conventional computing paradigm of one multiply-accumulate (MAC) operation per device.
Integrated multi-operand optical neurons for scalable and hardware-efficient deep learning
The optical neural network (ONN) is a promising hardware platform for next-generation neuromorphic computing due to its high parallelism, low latency, and low energy consumption.
Pre-RMSNorm and Pre-CRMSNorm Transformers: Equivalent and Efficient Pre-LN Transformers
Experiments demonstrate that we can reduce the training and inference time of Pre-LN Transformers by 1% - 10%.
HEAT: Hardware-Efficient Automatic Tensor Decomposition for Transformer Compression
Transformers have attained superior performance in natural language processing and computer vision.
QuEst: Graph Transformer for Quantum Circuit Reliability Estimation
Specifically, the TorchQuantum library also supports using data-driven ML models to solve problems in quantum system research, such as predicting the impact of quantum noise on circuit fidelity and improving the quantum circuit compilation efficiency.
An Adversarial Active Sampling-based Data Augmentation Framework for Manufacturable Chip Design
These synthetic mask images will augment the original limited training dataset used to finetune the lithography model for improved performance.
NeurOLight: A Physics-Agnostic Neural Operator Enabling Parametric Photonic Device Simulation
In this work, for the first time, a physics-agnostic neural operator-based framework, dubbed NeurOLight, is proposed to learn a family of frequency-domain Maxwell PDEs for ultra-fast parametric photonic device simulation.
TAG: Learning Circuit Spatial Embedding From Layouts
Analog and mixed-signal (AMS) circuit designs still rely on human design expertise.
Delving into Effective Gradient Matching for Dataset Condensation
In this work, we delve into the gradient matching method from a comprehensive perspective and answer the critical questions of what, how, and where to match.
QOC: Quantum On-Chip Training with Parameter Shift and Gradient Pruning
Nevertheless, we find that due to the significant quantum errors (noises) on real machines, gradients obtained from naive parameter shift have low fidelity and thus degrading the training accuracy.
ELight: Enabling Efficient Photonic In-Memory Neurocomputing with Life Enhancement
With the recent advances in optical phase change material (PCM), photonic in-memory neurocomputing has demonstrated its superiority in optical neural network (ONN) designs with near-zero static power consumption, time-of-light latency, and compact footprint.
A compact butterfly-style silicon photonic-electronic neural chip for hardware-efficient deep learning
The optical neural network (ONN) is a promising hardware platform for next-generation neurocomputing due to its high parallelism, low latency, and low energy consumption.
Multi-Scale High-Resolution Vision Transformer for Semantic Segmentation
Therefore, we propose HRViT, which enhances ViTs to learn semantically-rich and spatially-precise multi-scale representations by integrating high-resolution multi-branch architectures with ViTs.
Ranked #24 on
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on Cityscapes val
L2ight: Enabling On-Chip Learning for Optical Neural Networks via Efficient in-situ Subspace Optimization
In this work, we propose a closed-loop ONN on-chip learning framework L2ight to enable scalable ONN mapping and efficient in-situ learning.
QuantumNAT: Quantum Noise-Aware Training with Noise Injection, Quantization and Normalization
Furthermore, to improve the robustness against noise, we propose noise injection to the training process by inserting quantum error gates to PQC according to realistic noise models of quantum hardware.
DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networks
The key contributions of this paper are a novel sample-efficient two-stage deep learning optimization framework leveraging RL actor-critic algorithms, and a recipe to extend it on large industrial circuits using critical device identification.
RoDesigner: Variation-Aware Optimization for Robust Analog Design with Multi-Task RL
Specifically, circuit optimizations under different variations are considered as a set of tasks.
Towards Efficient On-Chip Training of Quantum Neural Networks
The results demonstrate that our on-chip training achieves over 90% and 60% accuracy for 2-class and 4-class image classification tasks.
Delving into Macro Placement with Reinforcement Learning
In physical design, human designers typically place macros via trial and error, which is a Markov decision process.
Towards Memory-Efficient Neural Networks via Multi-Level in situ Generation
Deep neural networks (DNN) have shown superior performance in a variety of tasks.
QuantumNAS: Noise-Adaptive Search for Robust Quantum Circuits
Extensively evaluated with 12 QML and VQE benchmarks on 14 quantum computers, QuantumNAS significantly outperforms baselines.
Optimizer Fusion: Efficient Training with Better Locality and Parallelism
Machine learning frameworks adopt iterative optimizers to train neural networks.
SqueezeLight: Towards Scalable Optical Neural Networks with Multi-Operand Ring Resonators
Optical neural networks (ONNs) have demonstrated promising potentials for next-generation artificial intelligence acceleration with ultra-low latency, high bandwidth, and low energy consumption.
Efficient On-Chip Learning for Optical Neural Networks Through Power-Aware Sparse Zeroth-Order Optimization
Optical neural networks (ONNs) have demonstrated record-breaking potential in high-performance neuromorphic computing due to their ultra-high execution speed and low energy consumption.
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization
If the function is incompletely-specified, the implementation has to be true only on the care set.
PrivyNet: A Flexible Framework for Privacy-Preserving Deep Neural Network Training
Massive data exist among user local platforms that usually cannot support deep neural network (DNN) training due to computation and storage resource constraints.
