Search Results for author:
Found 5 papers, 0 papers with code
FPGA-based AI Smart NICs for Scalable Distributed AI Training Systems
The overhead of these collective communication operations in a distributed AI training system can bottleneck its performance, with more pronounced effects as the number of nodes increases.
Exploration of Low Numeric Precision Deep Learning Inference Using Intel FPGAs
This results in a trade-off between throughput and accuracy and can be tailored for different networks through various combinations of activation and weight data widths.
Distributed, Parallel, and Cluster Computing Hardware Architecture
WRPN: Wide Reduced-Precision Networks
We reduce the precision of activation maps (along with model parameters) and increase the number of filter maps in a layer, and find that this scheme matches or surpasses the accuracy of the baseline full-precision network.
WRPN: Training and Inference using Wide Reduced-Precision Networks
For computer vision applications, prior works have shown the efficacy of reducing the numeric precision of model parameters (network weights) in deep neural networks but also that reducing the precision of activations hurts model accuracy much more than reducing the precision of model parameters.
Accelerating Deep Convolutional Networks using low-precision and sparsity
To improve the compute efficiency, we focus on achieving high accuracy with extremely low-precision (2-bit) weight networks, and to accelerate the execution time, we aggressively skip operations on zero-values.
