Implementing CNN Layers on the Manticore Cluster-Based Many-Core Architecture

no code implementations • 16 Apr 2021 • Andreas Kurth, Fabian Schuiki, Luca Benini

This document presents implementations of fundamental convolutional neural network (CNN) layers on the Manticore cluster-based many-core architecture and discusses their characteristics and trade-offs.

LLHD: A Multi-level Intermediate Representation for Hardware Description Languages

1 code implementation • 7 Apr 2020 • Fabian Schuiki, Andreas Kurth, Tobias Grosser, Luca Benini

These tools are monolithic and mostly proprietary, disagree in their implementation of HDLs, and while many redundant IRs exists, no IR today can be used through the entire circuit design flow.

Programming Languages

Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22 nm FD-SOI

no code implementations • 2 Jun 2019 • Matheus Cavalcante, Fabian Schuiki, Florian Zaruba, Michael Schaffner, Luca Benini

In this paper, we present Ara, a 64-bit vector processor based on the version 0. 5 draft of RISC-V's vector extension, implemented in GlobalFoundries 22FDX FD-SOI technology.

Hardware Architecture

A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets

no code implementations • 19 Feb 2018 • Fabian Schuiki, Michael Schaffner, Frank K. Gürkaynak, Luca Benini

Most investigations into near-memory hardware accelerators for deep neural networks have primarily focused on inference, while the potential of accelerating training has received relatively little attention so far.

Distributed, Parallel, and Cluster Computing Hardware Architecture