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Found 9 papers, 1 papers with code
IMBUE: In-Memory Boolean-to-CUrrent Inference ArchitecturE for Tsetlin Machines
Non-volatile memory devices such as Resistive RAM (ReRAM) offer integrated switching and storage capabilities showing promising performance for ML applications.
A Temperature Independent Readout Circuit for ISFET-Based Sensor Applications
The ion-sensitive field-effect transistor (ISFET) is an emerging technology that has received much attention in numerous research areas, including biochemistry, medicine, and security applications.
Deceptive Logic Locking for Hardware Integrity Protection against Machine Learning Attacks
Hereby, the presented work offers a starting point for the design and evaluation of future-generation logic locking in the era of machine learning.
Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities
In the past decade, a lot of progress has been made in the design and evaluation of logic locking; a premier technique to safeguard the integrity of integrated circuits throughout the electronics supply chain.
ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework
With the growing demands of consumer electronic products, the computational requirements are increasing exponentially.
Hardware Architecture
An Investigation on Inherent Robustness of Posit Data Representation
Moreover, in 100% of the tested machine-learning applications, the accuracy of posit-implemented systems is higher than the classical floating-point-based ones.
Hardware Architecture
Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach
The first approach is based on a simple feedforward fully connected neural network.
ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems
Towards this end, we propose a novel Posit to fixed-point converter for enabling high-performance and energy-efficient hardware implementations for ANNs with minimal drop in the output accuracy.
CLARINET: A RISC-V Based Framework for Posit Arithmetic Empiricism
To the best of our knowledge, this is the first-ever integration of quire with a RISC-V core.
Hardware Architecture
