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Found 8 papers, 0 papers with code
To Spike or Not to Spike? A Quantitative Comparison of SNN and CNN FPGA Implementations
Due to their compute- and data-intensive nature, CNN accelerators have been developed as ASICs or on FPGAs.
EXPLAINABLE AI-BASED DYNAMIC FILTER PRUNING OF CONVOLUTIONAL NEURAL NETWORKS
Our proposed architecture for dynamic pruning can be deployed on different hardware platforms.
Proceedings of the DATE Friday Workshop on System-level Design Methods for Deep Learning on Heterogeneous Architectures (SLOHA 2021)
This volume contains the papers accepted at the first DATE Friday Workshop on System-level Design Methods for Deep Learning on Heterogeneous Architectures (SLOHA 2021), held virtually on February 5, 2021.
HipaccVX: Wedding of OpenVX and DSL-based Code Generation
OpenVX promises to solve this issue for computer vision applications with a royalty-free industry standard that is based on a graph-execution model.
Utilizing Explainable AI for Quantization and Pruning of Deep Neural Networks
We use these methods for (1) pruning of DNNs; this includes structured and unstructured pruning of \ac{CNN} filters pruning as well as pruning weights of fully connected layers, (2) non-uniform quantization of DNN weights using clustering algorithm; this is also referred to as Weight Sharing, and (3) integer-based mixed-precision quantization; this is where each layer of a DNN may use a different number of integer bits.
Automatic Optimization of Hardware Accelerators for Image Processing
Therefore, in previous work, we have shown that elevating the description of image algorithms to an even higher abstraction level, by using a Domain-Specific Language (DSL), can significantly cut down the complexity for designing such algorithms for FPGAs.
Proceedings of the DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015)
This volume contains the papers accepted at the DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015), held in Grenoble, France, March 13, 2015.
Code Generation for High-Level Synthesis of Multiresolution Applications on FPGAs
Multiresolution Analysis (MRA) is a mathematical method that is based on working on a problem at different scales.
