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Found 6 papers, 1 papers with code
SpikeSim: An end-to-end Compute-in-Memory Hardware Evaluation Tool for Benchmarking Spiking Neural Networks
To this end, we propose SpikeSim, a tool that can perform realistic performance, energy, latency and area evaluation of IMC-mapped SNNs.
COIN: Communication-Aware In-Memory Acceleration for Graph Convolutional Networks
Besides accelerating the computation using custom compute elements (CE) and in-memory computing, COIN aims at minimizing the intra- and inter-CE communication in GCN operations to optimize the performance and energy efficiency.
SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks
In-memory computing (IMC) on a monolithic chip for deep learning faces dramatic challenges on area, yield, and on-chip interconnection cost due to the ever-increasing model sizes.
Impact of On-Chip Interconnect on In-Memory Acceleration of Deep Neural Networks
In this technique, we use analytical models of NoC to evaluate end-to-end communication latency of any given DNN.
Structural Pruning in Deep Neural Networks: A Small-World Approach
Inspired by the observation that brain networks follow the Small-World model, we propose a novel structural pruning scheme, which includes (1) hierarchically trimming the network into a Small-World model before training, (2) training the network for a given dataset, and (3) optimizing the network for accuracy.
Towards Efficient Neural Networks On-a-chip: Joint Hardware-Algorithm Approaches
Machine learning algorithms have made significant advances in many applications.
