An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration

no code implementations • 4 May 2020 • Behzad Salami, Erhan Baturay Onural, Ismail Emir Yuksel, Fahrettin Koc, Oguz Ergin, Adrian Cristal Kestelman, Osman S. Unsal, Hamid Sarbazi-Azad, Onur Mutlu

We evaluate the reliability-power trade-off for such accelerators.

Image Classification Quantization

ORIGAMI: A Heterogeneous Split Architecture for In-Memory Acceleration of Learning

no code implementations • 30 Dec 2018 • Hajar Falahati, Pejman Lotfi-Kamran, Mohammad Sadrosadati, Hamid Sarbazi-Azad

To utilize available bandwidth without violating area and power budgets of logic layer, ORIGAMI comes with a computation-splitting compiler that divides an ML algorithm between in-memory accelerators and an out-of-the-memory platform in a balanced way and with minimum inter-communications.