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Subgraph Extraction-based Feedback-guided Iterative Scheduling for HLS
This paper proposes ISDC, a novel feedback-guided iterative system of difference constraints (SDC) scheduling algorithm for high-level synthesis (HLS).
HybridDNN: A Framework for High-Performance Hybrid DNN Accelerator Design and Implementation
To speedup Deep Neural Networks (DNN) accelerator design and enable effective implementation, we propose HybridDNN, a framework for building high-performance hybrid DNN accelerators and delivering FPGA-based hardware implementations.
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