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Found 10 papers, 1 papers with code
NonGEMM Bench: Understanding the Performance Horizon of the Latest ML Workloads with NonGEMM Workloads
Therefore, significant effort has been put to study and optimize the GEMM operators in order to speed up the execution of ML models.
Inter-Layer Scheduling Space Exploration for Multi-model Inference on Heterogeneous Chiplets
To address increasing compute demand from recent multi-model workloads with heavy models like large language models, we propose to deploy heterogeneous chiplet-based multi-chip module (MCM)-based accelerators.
DREAM: A Dynamic Scheduler for Dynamic Real-time Multi-model ML Workloads
Such dynamic behaviors introduce new challenges to the system software in an ML system since the overall system load is not completely predictable, unlike traditional ML workloads.
XRBench: An Extended Reality (XR) Machine Learning Benchmark Suite for the Metaverse
We hope that our work will stimulate research and lead to the development of a new generation of ML systems for XR use cases.
Multi-Scale High-Resolution Vision Transformer for Semantic Segmentation
Therefore, we propose HRViT, which enhances ViTs to learn semantically-rich and spatially-precise multi-scale representations by integrating high-resolution multi-branch architectures with ViTs.
Ranked #24 on
Semantic Segmentation
on Cityscapes val
Evaluating Spatial Accelerator Architectures with Tiled Matrix-Matrix Multiplication
There is a growing interest in custom spatial accelerators for machine learning applications.
Marvel: A Data-centric Compiler for DNN Operators on Spatial Accelerators
Searching for the optimal mappings is challenging because of the large space of mappings, and this challenge gets exacerbated with new operators and diverse accelerator configurations. To address this challenge, we propose a decoupled off-chip/on-chip approach that decomposes the mapping space into off-chip and on-chip subspaces, and first optimizes the off-chip subspace followed by the on-chip subspace.
Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Tasks
Neural Architecture Search (NAS) has demonstrated its power on various AI accelerating platforms such as Field Programmable Gate Arrays (FPGAs) and Graphic Processing Units (GPUs).
Heterogeneous Dataflow Accelerators for Multi-DNN Workloads
The results suggest that HDA is an alternative class of Pareto-optimal accelerators to RDA with strength in energy, which can be a better choice than RDAs depending on the use cases.
Distributed, Parallel, and Cluster Computing
Understanding Reuse, Performance, and Hardware Cost of DNN Dataflows: A Data-Centric Approach Using MAESTRO
The data partitioning and scheduling strategies used by DNN accelerators to leverage reuse and perform staging are known as dataflow, and they directly impact the performance and energy efficiency of DNN accelerator designs.
