no code implementations • 8 Sep 2019 • Hyunbin Park, Dohyun Kim, Shiho Kim
The key figure of merit in hardware inference accelerators is the number of multiply-and-accumulation operations per watt (MACs/W), where, the state-of-the-arts MACs/W remains several hundreds Giga-MACs/W.
Distributed, Parallel, and Cluster Computing Hardware Architecture Signal Processing
