no code implementations • 8 Oct 2022 • Yao Lu, Jide Zhang, Su Zheng, Zhen Li, Lingli Wang
In this paper, two approximate 3*3 multipliers are proposed and the synthesis results of the ASAP-7nm process library justify that they can reduce the area by 31. 38% and 36. 17%, and the power consumption by 36. 73% and 35. 66% compared with the exact multiplier, respectively.
2 code implementations • 20 Jan 2022 • Su Zheng, Zhen Li, Yao Lu, Jingbo Gao, Jide Zhang, Lingli Wang
We propose an optimization method for the automatic design of approximate multipliers, which minimizes the average error according to the operand distributions.