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Found 9 papers, 2 papers with code
O2V-Mapping: Online Open-Vocabulary Mapping with Neural Implicit Representation
Online construction of open-ended language scenes is crucial for robotic applications, where open-vocabulary interactive scene understanding is required.
HGS-Mapping: Online Dense Mapping Using Hybrid Gaussian Representation in Urban Scenes
However, integrating 3DGS into a street-view dense mapping framework still faces two challenges, including incomplete reconstruction due to the absence of geometric information beyond the LiDAR coverage area and extensive computation for reconstruction in large urban scenes.
Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs
High-level synthesis (HLS) notably speeds up the hardware design process by avoiding RTL programming.
MARS: Exploiting Multi-Level Parallelism for DNN Workloads on Adaptive Multi-Accelerator Systems
Along with the fast evolution of deep neural networks, the hardware system is also developing rapidly.
FlowMap: Path Generation for Automated Vehicles in Open Space Using Traffic Flow
However, how to cognize the ``road'' for automated vehicles where there is no well-defined ``roads'' remains an open problem.
SALO: An Efficient Spatial Accelerator Enabling Hybrid Sparse Attention Mechanisms for Long Sequences
However, the quadratic complexity of self-attention w. r. t the sequence length incurs heavy computational and memory burdens, especially for tasks with long sequences.
PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs
Specifically, in the graph construction flow, we introduce buffer insertion, datapath merging, graph trimming and feature annotation techniques to transform HLS designs into graph-structured data, which encode both intra-operation micro-architectures and inter-operation interconnects annotated with switching activities.
FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications
To reduce the design effort and achieve the right balance, we propose FP-Stereo for building high-performance stereo matching pipelines on FPGAs automatically.
Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis
Early and accurate congestion estimation is of great benefit to guide the optimization in HLS and improve the efficiency of implementation.
