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Found 8 papers, 4 papers with code
Pretraining Graph Neural Networks for few-shot Analog Circuit Modeling and Design
We show that pretraining GNNs on prediction of output node voltages can encourage learning representations that can be adapted to new unseen topologies or prediction of new circuit level properties with up to 10x more sample efficiency compared to a randomly initialized model.
Semi-supervised Offline Reinforcement Learning with Pre-trained Decision Transformers
In this paper, we investigate how we can leverage large reward-free (i. e. task-agnostic) offline datasets of prior interactions to pre-train agents that can then be fine-tuned using a small reward-annotated dataset.
Skill Preferences: Learning to Extract and Execute Robotic Skills from Human Feedback
A promising approach to solving challenging long-horizon tasks has been to extract behavior priors (skills) by fitting generative models to large offline datasets of demonstrations.
Hierarchical Few-Shot Imitation with Skill Transition Models
To this end, we present Few-shot Imitation with Skill Transition Models (FIST), an algorithm that extracts skills from offline data and utilizes them to generalize to unseen tasks given a few downstream demonstrations.
JUMBO: Scalable Multi-task Bayesian Optimization using Offline Data
Such a decomposition can dynamically control the reliability of information derived from the online and offline data and the use of pretrained neural networks permits scalability to large offline datasets.
GACEM: Generalized Autoregressive Cross Entropy Method for Multi-Modal Black Box Constraint Satisfaction
In this work we present a new method of black-box optimization and constraint satisfaction.
AutoCkt: Deep Reinforcement Learning of Analog Circuit Designs
Domain specialization under energy constraints in deeply-scaled CMOS has been driving the need for agile development of Systems on a Chip (SoCs).
Signal Processing
BagNet: Berkeley Analog Generator with Layout Optimizer Boosted with Deep Neural Networks
The discrepancy between post-layout and schematic simulation results continues to widen in analog design due in part to the domination of layout parasitics.
