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Found 5 papers, 1 papers with code
Design and Analysis of Novel Bit-flip Attacks and Defense Strategies for DNNs
In this paper, we present novel bit-flip attack (BFA) algorithms for DNNs, along with techniques for defending against the attack.
On the Impact of Partial Sums on Interconnect Bandwidth and Memory Accesses in a DNN Accelerator
The power, performance and area (PPA) constraints limit the number of MACs available in these accelerators.
Hardware Implementation of Hyperbolic Tangent Function using Catmull-Rom Spline Interpolation
Deep neural networks yield the state of the art results in many computer vision and human machine interface tasks such as object recognition, speech recognition etc.
Comparative Analysis of Polynomial and Rational Approximations of Hyperbolic Tangent Function for VLSI Implementation
Deep neural networks yield the state-of-the-art results in many computer vision and human machine interface applications such as object detection, speech recognition etc.
DRACO: Co-Optimizing Hardware Utilization, and Performance of DNNs on Systolic Accelerator
The number of processing elements (PEs) in a fixed-sized systolic accelerator is well matched for large and compute-bound DNNs; whereas, memory-bound DNNs suffer from PE underutilization and fail to achieve peak performance and energy efficiency.
