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Found 4 papers, 1 papers with code
Energy-efficient Task Adaptation for NLP Edge Inference Leveraging Heterogeneous Memory Architectures
Executing machine learning inference tasks on resource-constrained edge devices requires careful hardware-software co-design optimizations.
EdgeBERT: Sentence-Level Energy Optimizations for Latency-Aware Multi-Task NLP Inference
Transformer-based language models such as BERT provide significant accuracy improvement for a multitude of natural language processing (NLP) tasks.
CHIPKIT: An agile, reusable open-source framework for rapid test chip development
The current trend for domain-specific architectures (DSAs) has led to renewed interest in research test chips to demonstrate new specialized hardware.
Hardware Architecture
MASR: A Modular Accelerator for Sparse RNNs
The architecture is enhanced by a series of dynamic activation optimizations that enable compact storage, ensure no energy is wasted computing null operations, and maintain high MAC utilization for highly parallel accelerator designs.
