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Found 44 papers, 7 papers with code
Scalable Superconductor Neuron with Ternary Synaptic Connections for Ultra-Fast SNN Hardware
A novel high-fan-in differential superconductor neuron structure designed for ultra-high-performance Spiking Neural Network (SNN) accelerators is presented.
Memory-Efficient Vision Transformers: An Activation-Aware Mixed-Rank Compression Strategy
This paper addresses this memory limitation by introducing an activation-aware model compression methodology that uses selective low-rank weight tensor approximations of different layers to reduce the parameter count of ViTs.
Low-Precision Mixed-Computation Models for Inference on Edge
This paper presents a mixed-computation neural network processing approach for edge applications that incorporates low-precision (low-width) Posit and low-precision fixed point (FixP) number systems.
An On-Chip Trainable Neuron Circuit for SFQ-Based Spiking Neural Networks
We present an on-chip trainable neuron circuit.
Sensitivity-Aware Mixed-Precision Quantization and Width Optimization of Deep Neural Networks Through Cluster-Based Tree-Structured Parzen Estimation
As a result, our proposed method represents a leap forward in neural network design optimization, paving the way for quick model design and implementation in settings with limited resources, thereby propelling the potential of scalable deep learning solutions.
Brain Tumor Detection using Convolutional Neural Networks with Skip Connections
Different CNN architecture optimization techniques such as widening and deepening of the network and adding skip connections are applied to improve the accuracy of the network.
CrAFT: Compression-Aware Fine-Tuning for Efficient Visual Task Adaptation
Post-training compression techniques such as pruning and quantization can help lower deployment costs.
A Fast Training-Free Compression Framework for Vision Transformers
Token pruning has emerged as an effective solution to speed up the inference of large Transformer models.
Efficient Compilation and Mapping of Fixed Function Combinational Logic onto Digital Signal Processors Targeting Neural Network Inference and Utilizing High-level Synthesis
Recent efforts for improving the performance of neural network (NN) accelerators that meet today's application requirements have given rise to a new trend of logic-based NN inference relying on fixed function combinational logic.
Sparse Periodic Systolic Dataflow for Lowering Latency and Power Dissipation of Convolutional Neural Network Accelerators
This paper introduces the sparse periodic systolic (SPS) dataflow, which advances the state-of-the-art hardware accelerator for supporting lightweight neural networks.
A Fast and Efficient Conditional Learning for Tunable Trade-Off between Accuracy and Robustness
In this paper, we present a fast learnable once-for-all adversarial training (FLOAT) algorithm, which instead of the existing FiLM-based conditioning, presents a unique weight conditioned learning that requires no additional layer, thereby incurring no significant increase in parameter count, training time, or network latency compared to standard adversarial training.
BMPQ: Bit-Gradient Sensitivity Driven Mixed-Precision Quantization of DNNs from Scratch
Compared to the baseline FP-32 models, BMPQ can yield models that have 15. 4x fewer parameter bits with a negligible drop in accuracy.
Analyzing the Confidentiality of Undistillable Teachers in Knowledge Distillation
Knowledge distillation (KD) has recently been identified as a method that can unintentionally leak private information regarding the details of a teacher model to an unauthorized student.
HIRE-SNN: Harnessing the Inherent Robustness of Energy-Efficient Deep Spiking Neural Networks by Training with Crafted Input Noise
Low-latency deep spiking neural networks (SNNs) have become a promising alternative to conventional artificial neural networks (ANNs) because of their potential for increased energy efficiency on event-driven neuromorphic hardware.
Towards Low-Latency Energy-Efficient Deep SNNs via Attention-Guided Compression
To evaluate the merits of our approach, we performed experiments with variants of VGG and ResNet, on both CIFAR-10 and CIFAR-100, and VGG16 on Tiny-ImageNet. The SNN models generated through the proposed technique yield SOTA compression ratios of up to 33. 4x with no significant drops in accuracy compared to baseline unpruned counterparts.
NullaNet Tiny: Ultra-low-latency DNN Inference Through Fixed-function Combinational Logic
While there is a large body of research on efficient processing of deep neural networks (DNNs), ultra-low-latency realization of these models for applications with stringent, sub-microsecond latency requirements continues to be an unresolved, challenging problem.
A2P-MANN: Adaptive Attention Inference Hops Pruned Memory-Augmented Neural Networks
In this work, to limit the number of required attention inference hops in memory-augmented neural networks, we propose an online adaptive approach called A2P-MANN.
BRDS: An FPGA-based LSTM Accelerator with Row-Balanced Dual-Ratio Sparsification
In this paper, first, a hardware-friendly pruning algorithm for reducing energy consumption and improving the speed of Long Short-Term Memory (LSTM) neural network accelerators is presented.
A Tunable Robust Pruning Framework Through Dynamic Network Rewiring of DNNs
This paper presents a dynamic network rewiring (DNR) method to generate pruned deep neural network (DNN) models that are robust against adversarial attacks yet maintain high accuracy on clean images.
SynergicLearning: Neural Network-Based Feature Extraction for Highly-Accurate Hyperdimensional Learning
The proposed hybrid machine learning model has the same level of accuracy (i. e. $\pm$1%) as NNs while achieving at least 10% improvement in accuracy compared to HD learning models.
Deep-PowerX: A Deep Learning-Based Framework for Low-Power Approximate Logic Synthesis
This paper aims at integrating three powerful techniques namely Deep Learning, Approximate Computing, and Low Power Design into a strategy to optimize logic at the synthesis level.
NN-PARS: A Parallelized Neural Network Based Circuit Simulation Framework
The shrinking of transistor geometries as well as the increasing complexity of integrated circuits, significantly aggravate nonlinear design behavior.
CSM-NN: Current Source Model Based Logic Circuit Simulation -- A Neural Network Approach
The miniaturization of transistors down to 5nm and beyond, plus the increasing complexity of integrated circuits, significantly aggravate short channel effects, and demand analysis and optimization of more design corners and modes.
Efficient Training of Deep Convolutional Neural Networks by Augmentation in Embedding Space
However, fine-tuning a transfer model with data augmentation in the raw input space has a high computational cost to run the full network for every augmented input.
Pre-defined Sparsity for Low-Complexity Convolutional Neural Networks
We also compared the performance of our proposed architectures with that of ShuffleNet andMobileNetV2.
Runtime Deep Model Multiplexing for Reduced Latency and Energy Consumption Inference
The proposed algorithm allows the mobile device to detect the inputs that can be processed locally and the ones that require a larger model and should be sent a cloud server.
Energy-aware Scheduling of Jobs in Heterogeneous Cluster Systems Using Deep Reinforcement Learning
Energy consumption is one of the most critical concerns in designing computing devices, ranging from portable embedded systems to computer cluster systems.
Coarse2Fine: A Two-stage Training Method for Fine-grained Visual Classification
Small inter-class and large intra-class variations are the main challenges in fine-grained visual classification.
Optimizing Routerless Network-on-Chip Designs: An Innovative Learning-Based Framework
Machine learning applied to architecture design presents a promising opportunity with broad applications.
BottleNet: A Deep Learning Architecture for Intelligent Mobile Cloud Computing Services
Recent studies have shown the latency and energy consumption of deep neural networks can be significantly improved by splitting the network between the mobile device and cloud.
Towards Collaborative Intelligence Friendly Architectures for Deep Learning
In this approach, referred to as collaborative intelligence, intermediate features computed on the mobile device are offloaded to the cloud instead of the raw input data of the network, reducing the size of the data needed to be sent to the cloud.
Distributed, Parallel, and Cluster Computing
Approximate Logic Synthesis: A Reinforcement Learning-Based Technology Mapping Approach
Approximate Logic Synthesis (ALS) is the process of synthesizing and mapping a given Boolean network to a library of logic cells so that the magnitude/rate of error between outputs of the approximate and initial (exact) Boolean netlists is bounded from above by a predetermined total error threshold.
Hardware Architecture
Space Expansion of Feature Selection for Designing more Accurate Error Predictors
The results on various benchmarks demonstrate significant improvements in the prediction accuracy compared to the prior works which used only the accelerator inputs for the prediction.
Modeling Processor Idle Times in MPSoC Platforms to Enable Integrated DPM, DVFS, and Task Scheduling Subject to a Hard Deadline
Energy efficiency is one of the most critical design criteria for modern embedded systems such as multiprocessor system-on-chips (MPSoCs).
Operating Systems Distributed, Parallel, and Cluster Computing
Gradient Agreement as an Optimization Objective for Meta-Learning
Therefore, the degree of the contribution of a task to the parameter updates is controlled by introducing a set of weights on the loss function of the tasks.
A Meta-Learning Approach for Custom Model Training
Transfer-learning and meta-learning are two effective methods to apply knowledge learned from large data sources to new tasks.
NullaNet: Training Deep Neural Networks for Reduced-Memory-Access Inference
Deep neural networks have been successfully deployed in a wide variety of applications including computer vision and speech recognition.
Deploying Customized Data Representation and Approximate Computing in Machine Learning Applications
Lop allows researchers and designers to quickly compare quality of their models using various data representations and arithmetic operations in Python and contrast the hardware cost of viable representations by synthesizing them on their target platforms (e. g., FPGA or ASIC).
VIBNN: Hardware Acceleration of Bayesian Neural Networks
In this paper, we propose VIBNN, an FPGA-based hardware accelerator design for variational inference on BNNs.
JointDNN: An Efficient Training and Inference Engine for Intelligent Mobile Cloud Computing Services
Deep learning models are being deployed in many mobile intelligent applications.
A Hardware-Friendly Algorithm for Scalable Training and Deployment of Dimensionality Reduction Models on FPGA
With ever-increasing application of machine learning models in various domains such as image classification, speech recognition and synthesis, and health care, designing efficient hardware for these models has gained a lot of popularity.
FFT-Based Deep Learning Deployment in Embedded Systems
The large model size of DNNs, while providing excellent accuracy, also burdens the embedded platforms with intensive computation and storage.
High-Performance FPGA Implementation of Equivariant Adaptive Separation via Independence Algorithm for Independent Component Analysis
Independent Component Analysis (ICA) is a dimensionality reduction technique that can boost efficiency of machine learning models that deal with probability density functions, e. g. Bayesian neural networks.
HEBS: Histogram Equalization for Backlight Scaling
In this paper, a method is proposed for finding a pixel transformation function that maximizes backlight dimming while maintaining a pre-specified image distortion level for a liquid crystal display.
Other Computer Science
