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Found 3 papers, 0 papers with code
On the Distribution, Sparsity, and Inference-time Quantization of Attention Values in Transformers
This informs the design of an inference-time quantization technique using both pruning and log-scaled mapping which produces only a few (e. g. $2^3$) unique values.
Medusa: A Scalable Interconnect for Many-Port DNN Accelerators and Wide DRAM Controller Interfaces
To cope with the increasing demand and computational intensity of deep neural networks (DNNs), industry and academia have turned to accelerator technologies.
Maximizing CNN Accelerator Efficiency Through Resource Partitioning
Current approaches construct a single processor that computes the CNN layers one at a time; the processor is optimized to maximize the throughput at which the collection of layers is computed.
Hardware Architecture
