Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22 nm FD-SOI

no code implementations • 2 Jun 2019 • Matheus Cavalcante, Fabian Schuiki, Florian Zaruba, Michael Schaffner, Luca Benini

In this paper, we present Ara, a 64-bit vector processor based on the version 0. 5 draft of RISC-V's vector extension, implemented in GlobalFoundries 22FDX FD-SOI technology.

Hardware Architecture

A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets

no code implementations • 19 Feb 2018 • Fabian Schuiki, Michael Schaffner, Frank K. Gürkaynak, Luca Benini

Most investigations into near-memory hardware accelerators for deep neural networks have primarily focused on inference, while the potential of accelerating training has received relatively little attention so far.

Distributed, Parallel, and Cluster Computing Hardware Architecture