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Found 13 papers, 3 papers with code
SPADE: Sparse Pillar-based 3D Object Detection Accelerator for Autonomous Driving
3D object detection using point cloud (PC) data is essential for perception pipelines of autonomous driving, where efficient encoding is key to meeting stringent resource and latency requirements.
Defensive ML: Defending Architectural Side-channels with Adversarial Obfuscation
To address this problem, this paper explores using Adversarial Machine Learning (AML) methods as a defense at the computer architecture layer to obfuscate side channels.
BNS-GCN: Efficient Full-Graph Training of Graph Convolutional Networks with Partition-Parallelism and Random Boundary Node Sampling
Graph Convolutional Networks (GCNs) have emerged as the state-of-the-art method for graph-based learning tasks.
Ranked #1 on
Node Classification
on Reddit
PipeGCN: Efficient Full-Graph Training of Graph Convolutional Networks with Pipelined Feature Communication
Notably, little is known regarding the convergence rate of GCN training with both stale features and stale feature gradients.
Harmony: Overcoming the Hurdles of GPU Memory Capacity to Train Massive DNN Models on Commodity Servers
Deep neural networks (DNNs) have grown exponentially in size over the past decade, leaving only those who have massive datacenter-based resources with the ability to develop and train such models.
BDS-GCN: Efficient Full-Graph Training of Graph Convolutional Nets with Partition-Parallelism and Boundary Sampling
While it can be natural to leverage graph partition and distributed training for tackling this challenge, this direction has only been slightly touched on previously due to the unique challenge posed by the GCN structures, especially the excessive amount of boundary nodes in each partitioned subgraph, which can easily explode the required memory and communications for distributed training of GCNs.
Intra-layer Neural Architecture Search
This work addresses NAS challenges in a search space of weight connections within layers, specifically the large number of architecture variations compared to a high-level search space with predetermined layer types.
IOCA: High-Speed I/O-Aware LLC Management for Network-Centric Multi-Tenant Platform
In this paper, we argue that besides CPU cores, high-speed network I/O is also important for LLC management.
Hardware Architecture Operating Systems
Bit-Parallel Vector Composability for Neural Acceleration
This paper explores a different design style, where each unit is only responsible for a slice of the bit-level operations to interleave and combine the benefits of bit-level parallelism with the abundant data-level parallelism in deep neural networks.
Mixed-Signal Charge-Domain Acceleration of Deep Neural networks through Interleaved Bit-Partitioned Arithmetic
Low-power potential of mixed-signal design makes it an alluring option to accelerate Deep Neural Networks (DNNs).
Hardware Architecture
GradiVeQ: Vector Quantization for Bandwidth-Efficient Gradient Aggregation in Distributed CNN Training
Data parallelism can boost the training speed of convolutional neural networks (CNN), but could suffer from significant communication costs caused by gradient aggregation.
Pipe-SGD: A Decentralized Pipelined SGD Framework for Distributed Deep Net Training
Distributed training of deep nets is an important technique to address some of the present day computing challenges like memory consumption and computational demands.
GANAX: A Unified MIMD-SIMD Acceleration for Generative Adversarial Networks
Even though there is a convolution stage in this operator, the inserted zeros lead to underutilization of the compute resources when a conventional convolution accelerator is employed.
