An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration

no code implementations • 4 May 2020 • Behzad Salami, Erhan Baturay Onural, Ismail Emir Yuksel, Fahrettin Koc, Oguz Ergin, Adrian Cristal Kestelman, Osman S. Unsal, Hamid Sarbazi-Azad, Onur Mutlu

We evaluate the reliability-power trade-off for such accelerators.

Image Classification Quantization

On the Resilience of Deep Learning for Reduced-voltage FPGAs

no code implementations • 26 Dec 2019 • Kamyar Givaki, Behzad Salami, Reza Hojabr, S. M. Reza Tayaranian, Ahmad Khonsari, Dara Rahmati, Saeid Gorgin, Adrian Cristal, Osman S. Unsal

This paper experimentally evaluates the resilience of the training phase of DNNs in the presence of voltage underscaling related faults of FPGAs, especially in on-chip memories.

TauRieL: Targeting Traveling Salesman Problem with a deep reinforcement learning inspired architecture

no code implementations • 14 May 2019 • Gorker Alp Malazgirt, Osman S. Unsal, Adrian Cristal Kestelman

In this paper, we propose TauRieL and target Traveling Salesman Problem (TSP) since it has broad applicability in theoretical and applied sciences.

reinforcement-learning Reinforcement Learning (RL) +1

Evaluating Built-in ECC of FPGA on-chip Memories for the Mitigation of Undervolting Faults

no code implementations • 29 Mar 2019 • Behzad Salami, Osman S. Unsal, Adrian Cristal Kestelman

In consequence, we achieve 40% of the BRAM power saving through undervolting below the minimum safe voltage level, with a negligible NN accuracy loss, thanks to the substantial fault coverage by the built-in ECC.