Search Results for author:
Found 7 papers, 1 papers with code
Dataflow-Aware PIM-Enabled Manycore Architecture for Deep Learning Workloads
However, as the complexity of Deep convolutional neural networks (DNNs) grows, we need to design a manycore architecture with multiple ReRAM-based processing elements (PEs) on a single chip.
FARe: Fault-Aware GNN Training on ReRAM-based PIM Accelerators
Experimental results demonstrate that FARe framework can restore GNN test accuracy by 47. 6% on faulty ReRAM hardware with a ~1% timing overhead compared to the fault-free counterpart.
SETGAN: Scale and Energy Trade-off GANs for Image Applications on Mobile Platforms
The key idea behind SETGAN for an image generation task is for a given input image, we train a GAN on a remote server and use the trained model on edge devices.
An Energy-Aware Online Learning Framework for Resource Management in Heterogeneous Platforms
To address this need, system-on-chips (SoC) that are at the heart of these devices provide a variety of control knobs, such as the number of active cores and their voltage/frequency levels.
Trading-off Accuracy and Energy of Deep Inference on Embedded Systems: A Co-Design Approach
Deep neural networks have seen tremendous success for different modalities of data including images, videos, and speech.
Learning-based Application-Agnostic 3D NoC Design for Heterogeneous Manycore Systems
Our results show that these generalized 3D NoCs only incur a 1. 8% (36-tile system) and 1. 1% (64-tile system) average performance loss compared to application-specific NoCs.
Machine Learning and Manycore Systems Design: A Serendipitous Symbiosis
Tight collaboration between experts of machine learning and manycore system design is necessary to create a data-driven manycore design framework that integrates both learning and expert knowledge.
