Search Results for author:
Found 25 papers, 6 papers with code
Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS
Existing large language models (LLMs) for register transfer level code generation face challenges like compilation failures and suboptimal power, performance, and area (PPA) efficiency.
ChIRAAG: ChatGPT Informed Rapid and Automated Assertion Generation
We designeda novel framework called ChIRAAG, based on OpenAI GPT4, to generate SVA assertions from natural language specifications.
Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimization
Logic synthesis, a pivotal stage in chip design, entails optimizing chip specifications encoded in hardware description languages like Verilog into highly efficient implementations using Boolean logic gates.
MaDEVIoT: Cyberattacks on EV Charging Can Disrupt Power Grid Operation
This paper examines the feasibility of demand-side cyberattacks on power grids launched via internet-connected high-power EV Charging Stations (EVCSs).
Towards the Imagenets of ML4EDA
Here we describe our experience curating two large-scale, high-quality datasets for Verilog code generation and logic synthesis.
Are Emily and Greg Still More Employable than Lakisha and Jamal? Investigating Algorithmic Hiring Bias in the Era of ChatGPT
We replicate this experiment on state-of-art LLMs (GPT-3. 5, Bard, Claude and Llama) to evaluate bias (or lack thereof) on gender, race, maternity status, pregnancy status, and political affiliation.
VeriGen: A Large Language Model for Verilog Code Generation
In this study, we explore the capability of Large Language Models (LLMs) to automate hardware design by generating high-quality Verilog code, a common language for designing and modeling digital systems.
Causative Cyberattacks on Online Learning-based Automated Demand Response Systems
Power utilities are adopting Automated Demand Response (ADR) to replace the costly fuel-fired generators and to preempt congestion during peak electricity demand.
LLM-assisted Generation of Hardware Assertions
As vulnerabilities in hardware can have severe implications on a system, there is a need for techniques to support security verification activities.
FLAG: Finding Line Anomalies (in code) with Generative AI
In this work, we explore the features that help LLMs in this classification and evaluate the performance of FLAG on known bugs.
INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Search
%Compared to prior work, INVICTUS is the first solution that uses a mix of RL and search methods joint with an online out-of-distribution detector to generate synthesis recipes over a wide range of benchmarks.
Chip-Chat: Challenges and Opportunities in Conversational Hardware Design
Modern hardware design starts with specifications provided in natural language.
ALMOST: Adversarial Learning to Mitigate Oracle-less ML Attacks via Synthesis Tuning
Oracle-less machine learning (ML) attacks have broken various logic locking schemes.
Benchmarking Large Language Models for Automated Verilog RTL Code Generation
Automating hardware design could obviate a significant amount of human error from the engineering process and lead to fewer errors.
Too Big to Fail? Active Few-Shot Learning Guided Logic Synthesis
Generating sub-optimal synthesis transformation sequences ("synthesis recipe") is an important problem in logic synthesis.
Pop Quiz! Can a Large Language Model Help With Reverse Engineering?
Large language models (such as OpenAI's Codex) have demonstrated impressive zero-shot multi-task capabilities in the software domain, including code explanation.
Examining Zero-Shot Vulnerability Repair with Large Language Models
We perform a large scale study of five commercially available, black-box, "off-the-shelf" LLMs, as well as an open-source model and our own locally-trained model, on a mix of synthetic, hand-crafted, and real-world security bug scenarios.
OpenABC-D: A Large-Scale Dataset For Machine Learning Guided Integrated Circuit Synthesis
Logic synthesis is a challenging and widely-researched combinatorial optimization problem during integrated circuit (IC) design.
Asleep at the Keyboard? Assessing the Security of GitHub Copilot's Code Contributions
The most notable of these comes in the form of the first self-described `AI pair programmer', GitHub Copilot, a language model trained over open-source GitHub code.
Cyber Insurance Against Cyberattacks on Electric Vehicle Charging Stations
In this paper, we propose cyber insurance for EVCSs to hedge the economic loss due to such cyberattacks and develop a data-driven cyber insurance design model for public EVCSs.
DAVE: Deriving Automatically Verilog from English
While specifications for digital systems are provided in natural language, engineers undertake significant efforts to translate them into the programming languages understood by compilers for digital systems.
Bias Busters: Robustifying DL-based Lithographic Hotspot Detectors Against Backdooring Attacks
Deep learning (DL) offers potential improvements throughout the CAD tool-flow, one promising application being lithographic hotspot detection.
Hardware Trojan Detection Using Controlled Circuit Aging
Combining IC aging with over-clocking produces a pattern of bit errors at the IC output by the induced timing violations.
NNoculation: Catching BadNets in the Wild
This paper proposes a novel two-stage defense (NNoculation) against backdoored neural networks (BadNets) that, repairs a BadNet both pre-deployment and online in response to backdoored test inputs encountered in the field.
Are Adversarial Perturbations a Showstopper for ML-Based CAD? A Case Study on CNN-Based Lithographic Hotspot Detection
There is substantial interest in the use of machine learning (ML) based techniques throughout the electronic computer-aided design (CAD) flow, particularly those based on deep learning.
