no code implementations • 3 Sep 2022 • Runbin Cai, Yi Fang, Zhifang Shi, Lin Dai, Guojun Han
To mitigate the impact of noise and interference on multi-level-cell (MLC) flash memory with the use of low-density parity-check (LDPC) codes, we propose a dynamic write-voltage design scheme considering the asymmetric property of raw bit error rate (RBER), which can obtain the optimal write voltage by minimizing a cost function.
