IMBUE: In-Memory Boolean-to-CUrrent Inference ArchitecturE for Tsetlin Machines

no code implementations • 22 May 2023 • Omar Ghazal, Simranjeet Singh, Tousif Rahman, Shengqi Yu, Yujin Zheng, Domenico Balsamo, Sachin Patkar, Farhad Merchant, Fei Xia, Alex Yakovlev, Rishad Shafik

Non-volatile memory devices such as Resistive RAM (ReRAM) offer integrated switching and storage capabilities showing promising performance for ML applications.

Single Storage Semi-Global Matching for Real Time Depth Processing

no code implementations • 7 Jul 2020 • Prathmesh Sawant, Yashwant Temburu, Mandar Datar, Imran Ahmed, Vinayak Shriniwas, Sachin Patkar

In this paper, we show the design and implementation of a stereo-vision system, which is based on FPGA-implementation of More Global Matching(MGM).

CLARINET: A RISC-V Based Framework for Posit Arithmetic Empiricism

1 code implementation • 30 May 2020 • Riya Jain, Niraj Sharma, Farhad Merchant, Sachin Patkar, Rainer Leupers

To the best of our knowledge, this is the first-ever integration of quire with a RISC-V core.

Hardware Architecture