no code implementations • 12 Feb 2024 • Vidya A. Chhabria, Wenjing Jiang, Sachin S. Sapatnekar
Engineering change orders (ECOs) in late stages make minimal design fixes to recover from timing shifts due to excessive IR drops.
no code implementations • 21 Dec 2023 • Yang Lv, Brandon R. Zink, Robert P. Bloom, Hüsrev Cılasun, Pravin Khanal, Salonik Resch, Zamshed Chowdhury, Ali Habiboglu, Weigang Wang, Sachin S. Sapatnekar, Ulya Karpuzcu, Jian-Ping Wang
Based on the experimental results, a suite of modeling has been developed to characterize the accuracy of CRAM computation.
no code implementations • 29 Jun 2023 • Hadi Esmaeilzadeh, Soroush Ghodrati, Andrew B. Kahng, Sean Kinzer, Susmita Dey Manasi, Sachin S. Sapatnekar, Zhiang Wang
The modeling effort of SimDIT comprehensively covers convolution and non-convolution operations of both CNN inference and training on a highly parameterizable hardware substrate.
no code implementations • 11 May 2023 • Vidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng, Sachin S. Sapatnekar
Inaccurate timing prediction wastes design effort, hurts circuit performance, and may lead to design failure.
no code implementations • 27 Oct 2021 • Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar
For PDN analysis, we propose two networks: (i) IREDGe: a full-chip static and dynamic IR drop predictor and (ii) EMEDGe: electromigration (EM) hotspot classifier based on input power, power grid distribution, and power pad distribution patterns.
no code implementations • 27 Oct 2021 • Vidya A. Chhabria, Sachin S. Sapatnekar
Power delivery network (PDN) design is a nontrivial, time-intensive, and iterative task.
no code implementations • 21 May 2021 • Sudipta Mondal, Susmita Dey Manasi, Kishor Kunal, S. Ramprasath, Sachin S. Sapatnekar
Graph neural networks (GNN) analysis engines are vital for real-world problems that use large graph models.
no code implementations • 30 Sep 2020 • Kishor Kunal, Jitesh Poojary, Tonmoy Dhar, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar
Analog layout synthesis requires some elements in the circuit netlist to be matched and placed symmetrically.
1 code implementation • 18 Sep 2020 • Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar
Computationally expensive temperature and power grid analyses are required during the design cycle to guide IC design.
1 code implementation • 9 May 2019 • Susmita Dey Manasi, Farhana Sharmin Snigdha, Sachin S. Sapatnekar
This work optimizes energy on a mobile client by partitioning CNN computations between in situ processing on the client and offloaded computations in the cloud.
Distributed, Parallel, and Cluster Computing Signal Processing
no code implementations • 10 Dec 2018 • Salonik Resch, S. Karen Khatamifard, Zamshed Iqbal Chowdhury, Masoud Zabihi, Zhengyang Zhao, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
Recently, binary neural networks have shown impressive efficiency and accuracy on image recognition data sets.
Emerging Technologies