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Found 5 papers, 0 papers with code
HeteroSwitch: Characterizing and Taming System-Induced Data Heterogeneity in Federated Learning
Such fragmentation introduces a new type of data heterogeneity in FL, namely \textit{system-induced data heterogeneity}, as each device generates distinct data depending on its hardware and software configurations.
A Novel ASIC Design Flow using Weight-Tunable Binary Neurons as Standard Cells
The binary neuron, referred to as an FTL (flash threshold logic) uses floating gate or flash transistors whose threshold voltages serve as a proxy for the weights of the neuron.
A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells
The unique aspect of the binary neuron is that it is implemented as a mixed-signal circuit that natively performs the inner-product and thresholding operation of an artificial binary neuron.
Enabling Incremental Knowledge Transfer for Object Detection at the Edge
However, we need a limited knowledge of the observed environment at inference time which can be learned using a shallow neural network (SHNN).
ELSA: A Throughput-Optimized Design of an LSTM Accelerator for Energy-Constrained Devices
The paper demonstrates that ELSA can achieve significant improvements in power, area and energy-efficiency when compared to the baseline design and several ASIC implementations reported in the literature, making it suitable for use in embedded systems and real-time applications.
