Search Results for author: Sasindu Wijeratne

Found 8 papers, 0 papers with code

PAHD: Perception-Action based Human Decision Making using Explainable Graph Neural Networks on SAR Images

no code implementations5 Jan 2024 Sasindu Wijeratne, Bingyi Zhang, Rajgopal Kannan, Viktor Prasanna, Carl Busart

This detailed information includes the SAR image features that contributed to the classification, the classification confidence, and the probability of the identified object being classified as a different object type or class.

Decision Making Object

Exploiting On-chip Heterogeneity of Versal Architecture for GNN Inference Acceleration

no code implementations4 Aug 2023 Paul Chen, Pavan Manjunath, Sasindu Wijeratne, Bingyi Zhang, Viktor Prasanna

To exploit data sparsity during inference, we devise a runtime kernel mapping strategy that dynamically assigns computation tasks to the PL and AIE based on data sparsity.

Graph Neural Network for Accurate and Low-complexity SAR ATR

no code implementations11 May 2023 Bingyi Zhang, Sasindu Wijeratne, Rajgopal Kannan, Viktor Prasanna, Carl Busart

In this work, we propose a graph neural network (GNN) model to achieve accurate and low-latency SAR ATR.

Towards Programmable Memory Controller for Tensor Decomposition

no code implementations17 Jul 2022 Sasindu Wijeratne, Ta-Yang Wang, Rajgopal Kannan, Viktor Prasanna

Implementing accelerators on Field Programmable Gate Array (FPGA) for kernels such as MTTKRP is attractive due to the energy efficiency and the inherent parallelism of FPGA.

Tensor Decomposition

Reconfigurable Low-latency Memory System for Sparse Matricized Tensor Times Khatri-Rao Product on FPGA

no code implementations18 Sep 2021 Sasindu Wijeratne, Rajgopal Kannan, Viktor Prasanna

This paper focuses on a multi-faceted memory system, which explores the spatial and temporal locality of the data structures of MTTKRP.

Tensor Decomposition

Programmable FPGA-based Memory Controller

no code implementations21 Aug 2021 Sasindu Wijeratne, Sanket Pattnaik, Zhiyu Chen, Rajgopal Kannan, Viktor Prasanna

Since developing memory controllers for different applications is time-consuming, this paper introduces a modular and programmable memory controller that can be configured for different target applications on available hardware resources.

Scheduling

Scalable High Performance SDN Switch Architecture on FPGA for Core Networks

no code implementations30 Oct 2019 Sasindu Wijeratne, Ashen Ekanayake, Sandaruwan Jayaweera, Danuka Ravishan, Ajith Pasqual

Due to the increasing heterogeneity in network user requirements, dynamically varying day to day network traffic patterns and delay in-network service deployment, there is a huge demand for scalability and flexibility in modern networking infrastructure, which in return has paved way for the introduction of Software Defined Networking (SDN) in core networks.

Vocal Bursts Intensity Prediction

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