Search Results for author: Siva Satyendra Sahoo

Found 3 papers, 0 papers with code

AxOMaP: Designing FPGA-based Approximate Arithmetic Operators using Mathematical Programming

no code implementations23 Sep 2023 Siva Satyendra Sahoo, Salim Ullah, Akash Kumar

Compared to traditional evolutionary algorithms-based optimization, we report up to 21% improvement in the hypervolume, for joint optimization of PPA and BEHAV, in the design of signed 8-bit multipliers.

Evolutionary Algorithms

AxOCS: Scaling FPGA-based Approximate Operators using Configuration Supersampling

no code implementations22 Sep 2023 Siva Satyendra Sahoo, Salim Ullah, Soumyo Bhattacharjee, Akash Kumar

The rising usage of AI and ML-based processing across application domains has exacerbated the need for low-cost ML implementation, specifically for resource-constrained embedded systems.

ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems

no code implementations24 Oct 2020 Suresh Nambi, Salim Ullah, Aditya Lohana, Siva Satyendra Sahoo, Farhad Merchant, Akash Kumar

Towards this end, we propose a novel Posit to fixed-point converter for enabling high-performance and energy-efficient hardware implementations for ANNs with minimal drop in the output accuracy.

Network Pruning

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