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Found 6 papers, 0 papers with code
COIN: Communication-Aware In-Memory Acceleration for Graph Convolutional Networks
Besides accelerating the computation using custom compute elements (CE) and in-memory computing, COIN aims at minimizing the intra- and inter-CE communication in GCN operations to optimize the performance and energy efficiency.
SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks
In-memory computing (IMC) on a monolithic chip for deep learning faces dramatic challenges on area, yield, and on-chip interconnection cost due to the ever-increasing model sizes.
FLASH: Fast Neural Architecture Search with Hardware Optimization
This paper proposes FLASH, a very fast NAS methodology that co-optimizes the DNN accuracy and performance on a real hardware platform.
Impact of On-Chip Interconnect on In-Memory Acceleration of Deep Neural Networks
In this technique, we use analytical models of NoC to evaluate end-to-end communication latency of any given DNN.
Online Adaptive Learning for Runtime Resource Management of Heterogeneous SoCs
Dynamic resource management has become one of the major areas of research in modern computer and communication system design due to lower power consumption and higher performance demands.
An Energy-Aware Online Learning Framework for Resource Management in Heterogeneous Platforms
To address this need, system-on-chips (SoC) that are at the heart of these devices provide a variety of control knobs, such as the number of active cores and their voltage/frequency levels.
