no code implementations • 15 Dec 2023 • Jonathan Sanderson, Syed Rafay Hasan
To validate our proposed methodology, LEAP, a simple image enhancement algorithm, histogram equalization, is designed and integrated in the FPGA fabric along with Xilinx's Deep Processing Unit (DPU).
no code implementations • 15 Dec 2023 • Jonathan Sanderson, Syed Rafay Hasan
To fill this knowledge gap, we provide a case study on two popular image enhancement algorithms, Histogram Equalization (HE) and Retinex (RX).
no code implementations • 18 Feb 2022 • Adewale Adeyemo, Travis Sandefur, Tolulope A. Odetola, Syed Rafay Hasan
We further propose a library-based approach to design scalable and dynamic distributed CNN inference on the fly leveraging partial-reconfiguration techniques, which is particularly suitable for resource-constrained edge devices.
no code implementations • 22 Sep 2021 • Adewale Adeyemo, Faiq Khalid, Tolulope A. Odetola, Syed Rafay Hasan
Similar to traditional CNNs, CapsNet is also vulnerable to several malicious attacks, as studied by several researchers in the literature.
no code implementations • 13 Jul 2021 • Hawzhin Mohammed, Tolulope A. Odetola, Nan Guo, Syed Rafay Hasan
In this paper, dynamic deployment of Convolutional Neural Network (CNN) architecture is proposed utilizing only IoT-level devices.
no code implementations • 13 Jun 2021 • Tolulope Odetola, Faiq Khalid, Travis Sandefur, Hawzhin Mohammed, Syed Rafay Hasan
Since in horizontal collaboration of RC AIoT devices different sections of CNN architectures are outsourced to different untrusted third parties, the attacker may not know the input image, but it has access to the layer-by-layer output feature maps information for the assigned sections of the CNN architecture.
no code implementations • 16 Mar 2021 • Tolulope A. Odetola, Syed Rafay Hasan
Security of inference phase deployment of Convolutional neural network (CNN) into resource constrained embedded systems (e. g. low end FPGAs) is a growing research area.
no code implementations • 21 Nov 2020 • Faiq Khalid, Syed Rafay Hasan, Sara Zia, Osman Hasan, Falah Awwad, Muhammad Shafique
To reduce the overhead of data acquisition, we propose a single power-port current acquisition block using current sensors in time-division multiplexing, which increases accuracy while incurring reduced area overhead.
no code implementations • 16 Jun 2020 • Hawzhin Mohammed, Tolulope A. Odetola, Syed Rafay Hasan
The deployment of CNN on resource-constrained edge devices have proved challenging.
no code implementations • 14 Nov 2019 • Tolulope A. Odetola, Katie M. Groves, Syed Rafay Hasan
To the best of our knowledge this is the first work that proposes a 2-Level 3-Way (2L-3W) hardware-software co-verification methodology and provides a step-by-step guide for the successful mapping, deployment and verification of DLA on FPGA boards.
no code implementations • 5 Nov 2019 • Tolulope A. Odetola, Ogheneuriri Oderhohwo, Syed Rafay Hasan
In this paper, we propose a methodology that solves this problem by extending the capability of existing multi-label classification and provide models with lower latency that requires smaller memory size when deployed on edge devices.
no code implementations • 2 Nov 2019 • Tolulope A. Odetola, Hawzhin Raoof Mohammed, Syed Rafay Hasan
In this paper, we introduce a hardware Trojan attack called Input Interception Attack (IIA).
no code implementations • 4 Nov 2018 • Faiq Khalid, Syed Rafay Hasan, Osman Hasan, Muhammad Shafique
We present a run-time methodology for HT detection that employs a multi-parameter statistical traffic modeling of the communication channel in a given System-on-Chip (SoC), named as SIMCom.