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Found 10 papers, 0 papers with code
DRESS: Dynamic REal-time Sparse Subnets
The limited and dynamically varied resources on edge devices motivate us to deploy an optimized deep neural network that can adapt its sub-networks to fit in different resource constraints.
Memory-Oriented Design-Space Exploration of Edge-AI Hardware for XR Applications
Low-Power Edge-AI capabilities are essential for on-device extended reality (XR) applications to support the vision of Metaverse.
Distributed On-Sensor Compute System for AR/VR Devices: A Semi-Analytical Simulation Framework for Power Estimation
Augmented Reality/Virtual Reality (AR/VR) glasses are widely foreseen as the next generation computing platform.
Power-of-Two Quantization for Low Bitwidth and Hardware Compliant Neural Networks
Eventually, the experiments showed that for low bit width precision, non-uniform quantization performs better than uniform, and at the same time, PoT quantization vastly reduces the computational complexity of the neural network.
A Comprehensive Analysis on Adversarial Robustness of Spiking Neural Networks
In this work, we present, for the first time, a comprehensive analysis of the behavior of more bio-plausible networks, namely Spiking Neural Network (SNN) under state-of-the-art adversarial tests.
Enabling Spike-based Backpropagation for Training Deep Neural Network Architectures
Spiking Neural Networks (SNNs) have recently emerged as a prominent neural computing paradigm.
Incremental Learning in Deep Convolutional Neural Networks Using Partial Network Sharing
We propose an efficient training methodology and incrementally growing DCNN to learn new tasks while sharing part of the base network.
Gabor Filter Assisted Energy Efficient Fast Learning Convolutional Neural Networks
This combination creates a balanced system that gives better training performance in terms of energy and time, compared to the standalone CNN (without any Gabor kernels), in exchange for tolerable accuracy degradation.
Multiplier-less Artificial Neurons Exploiting Error Resiliency for Energy-Efficient Neural Computing
Multipliers consume most of the processing energy in the digital neurons, and thereby in the hardware implementations of artificial neural networks.
Significance Driven Hybrid 8T-6T SRAM for Energy-Efficient Synaptic Storage in Artificial Neural Networks
Our analysis on a widely used digit recognition dataset indicates that the voltage can be scaled by 200mV from the nominal operating voltage (950mV) for practically no loss (less than 0. 5%) in accuracy (22nm predictive technology).
