Search Results for author: Vidya A. Chhabria

Found 5 papers, 1 papers with code

IR-Aware ECO Timing Optimization Using Reinforcement Learning

no code implementations12 Feb 2024 Vidya A. Chhabria, Wenjing Jiang, Sachin S. Sapatnekar

Engineering change orders (ECOs) in late stages make minimal design fixes to recover from timing shifts due to excessive IR drops.

reinforcement-learning Reinforcement Learning (RL) +1

A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route

no code implementations11 May 2023 Vidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng, Sachin S. Sapatnekar

Inaccurate timing prediction wastes design effort, hurts circuit performance, and may lead to design failure.

Encoder-Decoder Networks for Analyzing Thermal and Power Delivery Networks

no code implementations27 Oct 2021 Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar

For PDN analysis, we propose two networks: (i) IREDGe: a full-chip static and dynamic IR drop predictor and (ii) EMEDGe: electromigration (EM) hotspot classifier based on input power, power grid distribution, and power pad distribution patterns.

Translation

Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks

1 code implementation18 Sep 2020 Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar

Computationally expensive temperature and power grid analyses are required during the design cycle to guide IC design.

Translation

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