Search Results for author: Vishal Saxena

Found 10 papers, 1 papers with code

Compact Modeling and Rapid Simulation of Silicon Photonic Micro-Disk and Ring Modulators

no code implementations23 Nov 2023 Vishal Saxena, Md Jubayer Shawon

Compact modeling of static and transient dynamics of these modulators is important for co-simulation with CMOS drivers and wavelength stabilization circuits.

Continuous Learning in a Single-Incremental-Task Scenario with Spike Features

no code implementations3 May 2020 Ruthvik Vaila, John Chiasson, Vishal Saxena

Deep Neural Networks (DNNs) have two key deficiencies, their dependence on high precision computing and their inability to perform sequential learning, that is, when a DNN is trained on a first task and the same DNN is trained on the next task it forgets the first task.

Deep Convolutional Spiking Neural Networks for Image Classification

no code implementations28 Mar 2019 Ruthvik Vaila, John Chiasson, Vishal Saxena

Spiking neural networks are biologically plausible counterparts of the artificial neural networks, artificial neural networks are usually trained with stochastic gradient descent and spiking neural networks are trained with spike timing dependant plasticity.

Classification General Classification +1

Energy-Efficient CMOS Memristive Synapses for Mixed-Signal Neuromorphic System-on-a-Chip

no code implementations7 Feb 2018 Vishal Saxena, Xinyu Wu, Kehan Zhu

Emerging non-volatile memory (NVM), or memristive, devices promise energy-efficient realization of deep learning, when efficiently integrated with mixed-signal integrated circuits on a CMOS substrate.

Dendritic-Inspired Processing Enables Bio-Plausible STDP in Compound Binary Synapses

no code implementations9 Jan 2018 Xinyu Wu, Vishal Saxena

Brain-inspired learning mechanisms, e. g. spike timing dependent plasticity (STDP), enable agile and fast on-the-fly adaptation capability in a spiking neural network.

Enabling Bio-Plausible Multi-level STDP using CMOS Neurons with Dendrites and Bistable RRAMs

no code implementations5 Dec 2016 Xinyu Wu, Vishal Saxena

Large-scale integration of emerging nanoscale non-volatile memory devices, e. g. resistive random-access memory (RRAM), can enable a new generation of neuromorphic computers that can solve a wide range of machine learning problems.

A CMOS Spiking Neuron for Dense Memristor-Synapse Connectivity for Brain-Inspired Computing

no code implementations2 Jun 2015 Xinyu Wu, Vishal Saxena, Kehan Zhu

Neuromorphic systems that densely integrate CMOS spiking neurons and nano-scale memristor synapses open a new avenue of brain-inspired computing.

Homogeneous Spiking Neuromorphic System for Real-World Pattern Recognition

no code implementations2 Jun 2015 Xinyu Wu, Vishal Saxena, Kehan Zhu

A neuromorphic chip that combines CMOS analog spiking neurons and memristive synapses offers a promising solution to brain-inspired computing, as it can provide massive neural network parallelism and density.

A CMOS Spiking Neuron for Brain-Inspired Neural Networks with Resistive Synapses and In-Situ Learning

no code implementations28 May 2015 Xinyu Wu, Vishal Saxena, Kehan Zhu, Sakkarapani Balagopal

Nanoscale resistive memories are expected to fuel dense integration of electronic synapses for large-scale neuromorphic system.

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