Search Results for author:
Found 10 papers, 2 papers with code
Radial Networks: Dynamic Layer Routing for High-Performance Large Language Models
In this work, we explore the practicality of layer sparsity by profiling residual connections and establish the relationship between model depth and layer sparsity.
Encodings for Prediction-based Neural Architecture Search
Building on our study, we present our predictor \textbf{FLAN}: \textbf{Fl}ow \textbf{A}ttention for \textbf{N}AS.
On Latency Predictors for Neural Architecture Search
We then design a general latency predictor to comprehensively study (1) the predictor architecture, (2) NN sample selection methods, (3) hardware device representations, and (4) NN operation encoding schemes.
Multi-Predict: Few Shot Predictors For Efficient Neural Architecture Search
Many hardware-aware neural architecture search (NAS) methods have been developed to optimize the topology of neural networks (NN) with the joint objectives of higher accuracy and lower latency.
EZNAS: Evolving Zero Cost Proxies For Neural Architecture Scoring
Our methodology efficiently discovers an interpretable and generalizable zero-cost proxy that gives state of the art score-accuracy correlation on all datasets and search spaces of NASBench-201 and Network Design Spaces (NDS).
A Genetic Programming Approach To Zero-Shot Neural Architecture Ranking
Neural networks are becoming increasingly ubiquitous in a wide range of use cases.
Automatic Speech Recognition
Automatic Speech Recognition (ASR)
+4
RHNAS: Realizable Hardware and Neural Architecture Search
The rapidly evolving field of Artificial Intelligence necessitates automated approaches to co-design neural network architecture and neural accelerators to maximize system efficiency and address productivity challenges.
Exposing Hardware Building Blocks to Machine Learning Frameworks
We focus on how to design topologies that complement such a view of neurons, how to automate such a strategy of neural network design, and inference of such networks on Xilinx FPGAs.
LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applications
Deployment of deep neural networks for applications that require very high throughput or extremely low latency is a severe computational challenge, further exacerbated by inefficiencies in mapping the computation to hardware.
HadaNets: Flexible Quantization Strategies for Neural Networks
On-board processing elements on UAVs are currently inadequate for training and inference of Deep Neural Networks.
