1 code implementation • 25 May 2023 • Zhengyuan Shi, Hongyang Pan, Sadaf Khan, Min Li, Yi Liu, Junhua Huang, Hui-Ling Zhen, Mingxuan Yuan, Zhufei Chu, Qiang Xu
Circuit representation learning aims to obtain neural representations of circuit elements and has emerged as a promising research direction that can be applied to various EDA and logic reasoning tasks.
no code implementations • 18 Apr 2023 • Zhiyuan Yan, Min Li, Zhengyuan Shi, Wenjie Zhang, Yingcong Chen, Hongce Zhang
Boolean satisfiability problem (SAT) is fundamental to many applications.
no code implementations • 27 Feb 2023 • Sadaf Khan, Zhengyuan Shi, Min Li, Qiang Xu
Circuit representation learning is a promising research direction in the electronic design automation (EDA) field.
no code implementations • 2 Sep 2022 • Zhengyuan Shi, Min Li, Yi Liu, Sadaf Khan, Junhua Huang, Hui-Ling Zhen, Mingxuan Yuan, Qiang Xu
This paper introduces SATformer, a novel Transformer-based approach for the Boolean Satisfiability (SAT) problem.
1 code implementation • 7 Jun 2022 • Zhengyuan Shi, Min Li, Sadaf Khan, Liuzheng Wang, Naixing Wang, Yu Huang, Qiang Xu
Unlike previous learning-based solutions that formulate the TPI task as a supervised-learning problem, we train a novel DRL agent, instantiated as the combination of a graph neural network (GNN) and a Deep Q-Learning network (DQN), to maximize the test coverage improvement.
no code implementations • 27 May 2022 • Min Li, Zhengyuan Shi, Qiuxia Lai, Sadaf Khan, Shaowei Cai, Qiang Xu
Based on this observation, we approximate the SAT solving procedure with a conditional generative model, leveraging a novel directed acyclic graph neural network (DAGNN) with two polarity prototypes for conditional SAT modeling.
1 code implementation • 26 Nov 2021 • Min Li, Sadaf Khan, Zhengyuan Shi, Naixing Wang, Yu Huang, Qiang Xu
We propose DeepGate, a novel representation learning solution that effectively embeds both logic function and structural information of a circuit as vectors on each gate.
1 code implementation • 26 Nov 2021 • Min Li, Zhengyuan Shi, Zezhong Wang, Weiwei Zhang, Yu Huang, Qiang Xu
The proposed GA-guided XORNets also allows reducing the number of control bits, and the total testing time decreases by 20. 78% on average and up to 47. 09% compared to the existing design without sacrificing test coverage.