Search Results for author:
Found 15 papers, 5 papers with code
FL-NAS: Towards Fairness of NAS for Resource Constrained Devices via Large Language Models
Neural Architecture Search (NAS) has become the de fecto tools in the industry in automating the design of deep neural networks for various applications, especially those driven by mobile and edge devices with limited computing resources.
U-SWIM: Universal Selective Write-Verify for Computing-in-Memory Neural Accelerators
In our research, we illustrate that only a small fraction of weights need this write-verify treatment for the corresponding devices and the DNN accuracy can be preserved, yielding a notable programming acceleration.
Compute-in-Memory based Neural Network Accelerators for Safety-Critical Systems: Worst-Case Scenarios and Protections
In this study, we define the problem of pinpointing the worst-case performance of CiM DNN accelerators affected by device variations.
FRCSyn Challenge at WACV 2024:Face Recognition Challenge in the Era of Synthetic Data
Despite the widespread adoption of face recognition technology around the world, and its remarkable performance on current benchmarks, there are still several challenges that must be covered in more detail.
Improving Realistic Worst-Case Performance of NVCiM DNN Accelerators through Training with Right-Censored Gaussian Noise
In this work, we propose to use the k-th percentile performance (KPP) to capture the realistic worst-case performance of DNN models executing on CiM accelerators.
On the Viability of using LLMs for SW/HW Co-Design: An Example in Designing CiM DNN Accelerators
In this study, we present a novel approach that leverages Large Language Models (LLMs) to address this issue.
Negative Feedback Training: A Novel Concept to Improve Robustness of NVCIM DNN Accelerators
However, the stochastic nature and intrinsic variations of NVM devices often result in performance degradation in DNN inference.
Computing-In-Memory Neural Network Accelerators for Safety-Critical Systems: Can Small Device Variations Be Disastrous?
In this work, we formulate the problem of determining the worst-case performance of CiM DNN accelerators under the impact of device variations.
A Semi-Decoupled Approach to Fast and Optimal Hardware-Software Co-Design of Neural Accelerators
We first perform neural architecture search to obtain a small set of optimal architectures for one accelerator candidate.
SWIM: Selective Write-Verify for Computing-in-Memory Neural Accelerators
In this work, we show that it is only necessary to select a small portion of the weights for write-verify to maintain the DNN accuracy, thus achieving significant speedup.
RADARS: Memory Efficient Reinforcement Learning Aided Differentiable Neural Architecture Search
To the best of the authors' knowledge, this is the first DNAS framework that can handle large search spaces with bounded memory usage.
Uncertainty Modeling of Emerging Device-based Computing-in-Memory Neural Accelerators with Application to Neural Architecture Search
Emerging device-based Computing-in-memory (CiM) has been proved to be a promising candidate for high-energy efficiency deep neural network (DNN) computations.
Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Tasks
Neural Architecture Search (NAS) has demonstrated its power on various AI accelerating platforms such as Field Programmable Gate Arrays (FPGAs) and Graphic Processing Units (GPUs).
Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators
In this paper, we are the first to bring the computing-in-memory architecture, which can easily transcend the memory wall, to interplay with the neural architecture search, aiming to find the most efficient neural architectures with high network accuracy and maximized hardware efficiency.
When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies
We are then able to analytically explore the weakness of a network and summarize the key findings for the impact of SIPP on different types of bits in a floating point parameter, layer-wise robustness within the same network and impact of network depth.
