A Highly Parallel FPGA Implementation of Sparse Neural Network Training

31 May 2018Sourya DeyDiandian ChenZongyang LiSouvik KunduKuan-Wen HuangKeith M. ChuggPeter A. Beerel

We demonstrate an FPGA implementation of a parallel and reconfigurable architecture for sparse neural networks, capable of on-chip training and inference. The network connectivity uses pre-determined, structured sparsity to significantly reduce complexity by lowering memory and computational requirements... (read more)

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