Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network based on Analog Resistive Synapse

16 Dec 2017Chih-Cheng ChangPin-Chun ChenTeyuh ChouI-Ting WangBoris HudecChe-Chia ChangChia-Ming TsaiTian-Sheuan ChangTuo-Hung Hou

Asymmetric nonlinear weight update is considered as one of the major obstacles for realizing hardware neural networks based on analog resistive synapses because it significantly compromises the online training capability. This paper provides new solutions to this critical issue through co-optimization with the hardware-applicable deep-learning algorithms... (read more)

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