RoDesigner: Variation-Aware Optimization for Robust Analog Design with Multi-Task RL
Analog/mixed-signal circuit design is one of the most complex and time-consuming stages in the chip design process. Due to various process, voltage, and temperature (PVT) variations from chip manufacturing, analog circuits inevitably suffer from performance degradations. Although there has been plenty of work on automating analog circuit design under the typical condition, limited research has been done on exploring robust designs under the real and unpredictable silicon variations. To address these challenges, we present RoDesigner, a robust circuit design framework that involves the variation information in the optimization process. Specifically, circuit optimizations under different variations are considered as a set of tasks. Similarities among tasks are leveraged and competitions are alleviated to realize a sample-efficient multi-task training. Moreover, RoDesigner prunes the task space before multi-task training to reduce simulation costs. In this way, RoDesigner can rapidly produce a set of circuit parameters that satisfies diverse constraints (e.g., gain, bandwidth, noise...) across variations. We compare our method with Bayesian optimization, evolutionary algorithm, and Deep Deterministic Policy Gradient (DDPG) and demonstrate that RoDesigner can significantly reduce required optimization time by14×-30×. We also show that RoDesigner’s circuit performance is as good as a state-of-the-art human design, while the design time is reduced from several days by an expert to an hour.
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