We also illustrate that the system offers 3. 46X reduction in latency and 77. 02X reduction in power consumption when compared to a custom CMOS digital design implemented at the same technology node.
In the $128\times128$ network, it is observed that the number of input patterns the multistate synapse can classify is $\simeq$ 2. 1x that of a simple binary synapse model, at a mean accuracy of $\geq$ 75% .
The spatial pooler architecture is synthesized on Xilinx ZYNQ-7, with 91. 16% classification accuracy for MNIST and 90\% accuracy for EUNF, with noise.