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Found 12 papers, 0 papers with code
Field of Groves: An Energy-Efficient Random Forest
In this work, we present a field of groves (FoG) implementation of random forests (RF) that achieves an accuracy comparable to CNNs and SVMs under tight energy budgets.
LEAF-QA: Locate, Encode & Attend for Figure Question Answering
LEAF-QA being constructed from real-world sources, requires a novel architecture to enable question answering.
The efficacy of various machine learning models for multi-class classification of RNA-seq expression data
When the features were reduced to a list of 20 genes, the ensemble algorithms maintained an accuracy above 95% as opposed to the clustering and classification models.
CUDA optimized Neural Network predicts blood glucose control from quantified joint mobility and anthropometrics
In this paper, we leveraged the power of Nvidia GPUs to parallelize all of the computation involved in training, to accelerate a backpropagation feed-forward neural network with one hidden layer using CUDA and C++.
Custom Tailored Suite of Random Forests for Prefetcher Adaptation
To close the gap between memory and processors, and in turn improve performance, there has been an abundance of work in the area of data/instruction prefetcher designs.
Efficient Sealable Protection Keys for RISC-V
Recently, Intel introduced a new hardware feature for intra-process memory isolation, called Memory Protection Keys (MPK), which enables a user-space process to switch the domains in an efficient way.
Cryptography and Security Hardware Architecture
Puppeteer: A Random Forest-based Manager for Hardware Prefetchers across the Memory Hierarchy
In this work, we propose Puppeteer, which is a hardware prefetcher manager that uses a suite of random forest regressors to determine at runtime which prefetcher should be ON at each level in the memory hierarchy, such that the prefetchers complement each other and we reduce the data/instruction access latency.
Leveraging Residue Number System for Designing High-Precision Analog Deep Neural Network Accelerators
In addition, we show that RNS can reduce the energy consumption of the data converters within an analog accelerator by several orders of magnitude compared to a regular fixed-point approach.
A Blueprint for Precise and Fault-Tolerant Analog Neural Networks
Our study demonstrates that analog accelerators utilizing the RNS-based approach can achieve ${\geq}99\%$ of FP32 accuracy for state-of-the-art DNN inference using data converters with only $6$-bit precision whereas a conventional analog core requires more than $8$-bit precision to achieve the same accuracy in the same DNNs.
Accelerating DNN Training With Photonics: A Residue Number System-Based Design
Photonic computing is a compelling avenue for performing highly efficient matrix multiplication, a crucial operation in Deep Neural Networks (DNNs).
Towards Efficient Hyperdimensional Computing Using Photonics
Over the past few years, silicon photonics-based computing has emerged as a promising alternative to CMOS-based computing for Deep Neural Networks (DNN).
Photonics for Sustainable Computing
Our analysis shows that photonics can reduce both operational and embodied carbon footprints with its high energy efficiency and at least 4$\times$ less fabrication carbon cost per unit area than 28 nm CMOS.
