no code implementations • ICLR 2020 • Léopold Cambier, Anahita Bhiwandiwalla, Ting Gong, Mehran Nekuii, Oguz H. Elibol, Hanlin Tang
This necessitates increased memory footprint and computational requirements for training.
no code implementations • 4 Oct 2019 • Kara Lamb, Garima Malhotra, Athanasios Vlontzos, Edward Wagstaff, Atılım Günes Baydin, Anahita Bhiwandiwalla, Yarin Gal, Alfredo Kalaitzis, Anthony Reina, Asti Bhatt
High energy particles originating from solar activity travel along the the Earth's magnetic field and interact with the atmosphere around the higher latitudes.
no code implementations • 3 Oct 2019 • Kara Lamb, Garima Malhotra, Athanasios Vlontzos, Edward Wagstaff, Atılım Günes Baydin, Anahita Bhiwandiwalla, Yarin Gal, Alfredo Kalaitzis, Anthony Reina, Asti Bhatt
We propose a novel architecture and loss function to predict 1 hour in advance the magnitude of phase scintillations within a time window of plus-minus 5 minutes with state-of-the-art performance.
no code implementations • ICLR Workshop LLD 2019 • Subarna Tripathi, Anahita Bhiwandiwalla, Alexei Bastidas, Hanlin Tang
Existing scene graph to image models have two stages: (1) a scene composition stage, and an (2) image generation stage.
no code implementations • 11 Jan 2019 • Subarna Tripathi, Anahita Bhiwandiwalla, Alexei Bastidas, Hanlin Tang
Generating realistic images from scene graphs asks neural networks to be able to reason about object relationships and compositionality.
1 code implementation • 24 Jan 2018 • Scott Cyphers, Arjun K. Bansal, Anahita Bhiwandiwalla, Jayaram Bobba, Matthew Brookhart, Avijit Chakraborty, Will Constable, Christian Convey, Leona Cook, Omar Kanawi, Robert Kimball, Jason Knight, Nikolay Korovaiko, Varun Kumar, Yixing Lao, Christopher R. Lishka, Jaikrishnan Menon, Jennifer Myers, Sandeep Aswath Narayana, Adam Procter, Tristan J. Webb
The current approach, which we call "direct optimization", requires deep changes within each framework to improve the training performance for each hardware backend (CPUs, GPUs, FPGAs, ASICs) and requires $\mathcal{O}(fp)$ effort; where $f$ is the number of frameworks and $p$ is the number of platforms.